Re : ENB and jitter of NI PXI-4461 board?

[Ov_metas]

Hello!

I have 2 questions concerning the NI PXI-4461 board:

1) I wonder the equivalent number of bit (ENB) of the ADCs of NI 4461 board? I know that they have 24-bit sigma-delat converters but does the ENB depend on the signal frequency or/and sampling frequency?

2) What is the jitter that affect the sampling frequency ?

I tanks you in advance,

Best regards,

Frédéric

[sarahbl]

Hi Frédéric,

You can find the information about the Effective Number of Bits (ENOB) on this KB [broken link removed]. This KB is written for 449x devices, but those card are also DSA cards with delta-sigma ADCs. So you can use it for your PXI 4461.

You can find the Total Harmonic Distortion Plus Noise (THD+N) you need to calculate the ENOB on page 9 in the specs.

About your second question, I am not sure to understand what you are asking. Can you explain it please ?

Best regards,

Sarah BL

[Ov_metas]

Hi Sarah,

Many thanks for your answare!

Following the informations you gave me, the ENOB at a sampling frequency of 200 kS/s on the range gain of 10 dB (+-3.16 V) is only 17.85 bit !!! The dynamic range DR is 110 dB (see page 8 of the specs) and the formula is ENOB = (DR - 1.7609) / 6.0206.

I understand the DR=110 dB is only the "typical" value but the resulting ENOB of 17.8 bit is well below the nominal 24 bit of resolution!!

Concerning my second question: with a sampling frequency of fs=200 kS/s, the board will give me a value every dt=1/fs=5 us. The jitter I am looking for is the stability of this dt!

I hope that my second question is clearer?

I thanks you in advance!

Best regards,

Frédéric

[dsb@NI]

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Following the informations you gave me, the ENOB at a sampling frequency of 200 kS/s on the range gain of 10 dB (+-3.16 V) is only 17.85 bit !!! The dynamic range DR is 110 dB (see page 8 of the specs) and the formula is ENOB = (DR - 1.7609) / 6.0206.

I understand the DR=110 dB is only the "typical" value but the resulting ENOB of 17.8 bit is well below the nominal 24 bit of resolution!!

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Yes, ~18 bit is much less than the nominal 24-bit resolution of the ADC, and this highlights the importance of good design of the analog front end AND setting the range of the channel appropriately for the signals you are trying to measure. 

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Concerning my second question: with a sampling frequency of fs=200 kS/s, the board will give me a value every dt=1/fs=5 us. The jitter I am looking for is the stability of this dt!

I hope that my second question is clearer?

Your question is clear. I don't see the clock jitter (or phase noise) specified in the 4461 module specifications though, and it is not a warranted spec verified during calibration. Out of curiosity, are you looking for the clock stability because you care about phase noise? Do you want to know what to expect, or would you prefer an experimental procedure to measure phase noise for your device?