synchronising DSA cards with FPGA

[Sahana]

Hi

We are integrating our  DSA and FPGA drivers using sample clock time base. The master-salve synchronization works well for multiple DSA cards. Sharing over sample clock between DSA and FPGA is not working.The code for this synchronisation of master with the slave is as  per the example vi in LV (National Instruments\LabVIEW 7.1\examples\DAQmx\Synchronization\Multi-Device.llb\Multi-Device Synch-Analog Input-Cont Acquisition.vi).

We have configured such that the FPGA vi waits for clock pulse from PXI star line (Oversample clock). But the  FPGA vi does not seem to realise any clock inputs in the PXI star line and keeps waiting at that point.. Is there any different configuration required either in DSA or FPGA vi’s for sharing the oversample clock .

Slot 2-6- DSA cards
Slot 7- PXI 7833R

Kindly  help us on this issue

Regards
Sahana

[reddog]

First, I wanted to mention that while the Multi-Device Synch-Analog Input-Cont Acquisition.vi will work, as of DAQmx 7.4, you can now create channels from multiple DSA devices in a single task.  When created within a single task, the driver will automatically take care of routing the appropriate clocks and triggers for you to achieve synchronization.  This may make your programming a little cleaner and easier. 

Second, the example you are using only takes care of synchronizing the DSA boards and doesn't export any clocks or triggers to any devices outside of the DAQmx driver.  To do this, you need to use the DAQmx Eport Signal Property Node to export the sample clock timebase from the device in slot 2 to the appropriate star trigger line.  The star trigger lines are listed in the I/O terminal control as PXI_Star0, PXI_Star1 ... PXI_Star12.  In order to see the star trigger lines in the I/O control, you will need to right click on the I/O control, select the I/O name filtering... menu, and ensure the Include Andvanced Terminals check box is selected.  PXI_Star0 corresponds to the star trigger line connecting slots 2 and 3, PXI_Star1 corresponds the star trigger line connecting slots 2 and 4, and so on.  In your case, you're trying to connect slots 2 and 7 so you'll need to use PXI_Star4.

The attached program illustrates creating channels from multiple devices in a single task as well as how to export the sample clock timebase to the designated star trigger line.

[Sahana]

Thanks for the valuable suggestion on the sharing of clock signals between the slot 2 master and the FPGA card in the slot 7.
The boards appear to sync well.

But further with another issue,we are also trying out the routing of the  start trigger from the master to the FPGA board.Earlier we had it the way it was in the example vi (DAQmx/synchronisation/Multiple device/cont acq.vi)which will give the start triggers for the different slave boards directly without any trigger lines.But later we  tried to export the start trigger from the master to PXI_Trig4 of the master board and tried to read the same in the FPGA(PXI_Trig4).But this also did not work.

Any inputs on the above?


Regards
Sahana

[Jack_A.]

Sahana -

Here's a good KB which has several different examples programs concerning how to synchronize DSA devices in DAQmx:

KB 3EE7N2NQ: Synchronizing DSA Devices in DAQmx

The last example should be the most interesting to you as it shows how to manually export different timing signals (such as the start trigger) from the DSA device to PXI_Trig lines.

-Jack

[Sahana]

Good day!

Thanks for the link.

Getting into the actual problem we ware facing,We have already tried to export the start trigger from the master (Export signl property node)
that is from slot2 to one of its trigger lines(PXI_Trig0-PXI_Trig7).But from my slot 7 this trigger needs to be realised.That is ,which of the trigger lines from slot2 is connected to which trigger line of slot7 ? (just like saying for the sample timebaseclock , it has to be routed to PXI_Star4 for realisation by slot 7 device). As my card in slot 7 is not responding to the start trigger when polling in its PXI trigger lines.


Regards
Sahana

[Giarc]

Sahana,

Just to clarify how the trigger bus is set up:

The Star trigger lines are unidirectional and go from slot 2 to each of the other slots starting with slot 3.  The names for the Star trigger lines are offset for each of the slots.  Slot 3 Star trigger line is called "PXI_Star0", Slot 4 is "PXI_Star1" and so on.  So the Star line for Slot 7 is "PXI_Star4".

The other PXI Trigger lines are bidirectional and go across the entire backplane so that any device in slot 2 or higher can source or receive triggers or other timing signals on these lines.  If you source StartTrigger from Slot2 on "PXI_Trig2", then you would listen for the StartTrigger on "PXI_Trig2" in any other slot(s).  So in your FPGA code for the 7833R in slot 7, you would poll "PXI_Trig2" to wait for the trigger.  You can only source the trigger to any given PXI_Trig line from one device (otherwise you risk damage to the hardware), but you can receive the trigger on multiple devices.

Craig