Sampling Analogic Signal cRIO 9201

[ocramm]

Hallo,

I succed to achive analogic signal and to create fpga and host program for cRIO 9004 and Analogic input module RIO9201!

I achive very well a 1 Hz signal but when I  increase frequency of my signal I lose in resolution!

the sampling rate of module is 800KS/s and I don't understand if it is a problem of  time in my software!

in the example of NI web site it isn't clear!

Thank you

Marco

[AlessioD]

The problem is indeed within your software.

You should consider looking at this

Tutorial

in order to understand how to program the FPGA and HOST parts of your application to achieve better performances.

I strongly recommend you call NI Italy Technical Support in order to receive the best support on this topic. There might be specific characteristics in your project that could require good programming skills in LV FPGA, and we would like to make your experience the best possible.

AlessioD

National Instruments

[ocramm]

Thank you, Alessio!

I call Nationale Support but they still recall me!

I follow the step in Tutorial High Speed Continuous Buffered Data Acquisition.

...........and there is a problem with FIFO,  I mean!

because the the led empy is always turn on and the FIFO read doesn't work!

I know that four value enter into FIFO write but FIFO read doesn't read them!

I believe the problem is here!

could you help me another time?

Thank you

[AlessioD]

Could you post your simple example here so that I can take a look at it?
Cheers,

AlessioD

[ocramm]

I used project in tutor page you sent me!

Here you are!

there is file project named "quattrosincro.lep"

file for FPGA named foursincro(fpga).vi and I think the problem is in FIFO read in this file

and file for Host named foursinco(host).vi

But do you know when NI Italy Technical Support recall me?

I called them yesterday morning and still nothing!

Mi dici quando potrò scriverti in italiano??

Thank you

Marco 

[ocramm]

I used project in tutor page you sent me!

Here you are!

there is file project named "quattrosincro.lep"

file for FPGA named foursincro(fpga).vi and I think the problem is in FIFO read in this file

and file for Host named foursinco(host).vi

But do you know when NI Italy Technical Support recall me?

I called them yesterday morning and still nothing!

Mi dici quando potrò scriverti in italiano??

Thank you

Marco