Error -61496 during FPGA compile

[MrJackHamilton]

Still having this compile error. This time I used the DevBoard CLIP - unaltered in any way. And recoded the Serial FPGA code to use PMOD1 pins 19 and 20 for Tx and Rx.

So this seems to be a real problem...

Regards

Jack Hamilton

[tannerite]

Hi Jack,

I was looking through your CLIP more thoroughly and diff'd your VHDL and XML files with files that were generated after importing your configuration file that gets generated in your CLIP files -- they are identical. I was thinking earlier that you may be instantiating an I2S core in the VHDL but it looks like all of your logic is in LabVIEW FPGA and you are just using DIO.

It also looks like you are not using the RS-232 serial port but are using two, regular DIO pins as a TX and RX and bit-banging that interface yourself, which should be fine but will not show up as a VISA resource in NI Linux Real-Time.

The error you are seeing is occurring during Code Generation before the Xilinx compilation process is occurring.

To summarize thus far, you have been able to successfully compile on a laptop running LabVIEW 2014 SP1 and Windows 7, but have this error when you try running it on a machine with Windows 8.1 and LabVIEW 2014 SP1 as well as wiping that machine and installing software identical to your laptop?

The attached MAX Technical Support Report is actually for your sbRIO-9651 which is not particularly helpful. Could you please generate MAX reports from your laptop and machine that you recently wiped that this issue is occurring on since one seems to work while the other does not?

Right now, I am trying to isolate variables on what appears to work and what is not. Have you ever seen this error on your laptop?

- Tanner

[tannerite]

Hi Jack,

I was able to reproduce by using your attached VI and socketed CLIP in a project I created. It looks like this is a reproducible bug on our end, but I think I found a potential workaround that resolved the error for me.

Open your VI and delete the "sbRIO-9651 Socket\nRS23_Tx_out" instances from your top loop and re-add them to your block diagram. I was then able to get past the code generation error that you are seeing.

Can you verify that this works on your end? In the meantime, we will look deeper into this.

- Tanner

[MrJackHamilton]

Tanner,

I2S: Yes we are hand coding the I2S in the FPGA directly.

RS232: Yes, we want RS232 thru the FPGA to acquire GPS data with I2S data with a GPS timestamp - hence we are not doing it RS232 in the RT side.

The error is occuring just after this screen....the Xlinix compile screen never shows.

Compile Successfully: NO, I cannot get the FPGA_SOM_Serial code to compile on ANY of my 3 systems, 2 of which are reliable. I can compile my I2S FPGA code without a problem on all the machines.

In desperation: To imported the DEVKIT Clip and relinked the FPGA_SOM_Serial.vi to the PMOD1 Pins 19 & 20..and STILL get his error on my laptop!.

I can successfully compile the PMOD1 pin 19 & 20 nodes on a blank FPGA VI....it seems when the I/O calls are put in the FPGA_SOM_Serial.vi it cannnot compile?.

I am running out of desperate things to try, I even pulled the FIFO's out to the Serial code incase there is some unhappyness there....not sure what to try next?.

Is there another FPGA Serial example?

[MrJackHamilton]

Tanner,

When I get back to my office computer - I will get you the MAX report for the machine.

Jack

[MrJackHamilton]

Tanner,

I will try now....

Jack

National InstrumentsCommunity

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Re: Error -61496 during FPGA compile

created by tannerite <https://decibel.ni.com/content/people/tannerite>

in /Hardware Developers Community for NI Single-Board RIO and System

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<https://decibel.ni.com/content/message/99799#99799>

[MrJackHamilton]

Tanner,

It looks like replacing all the I/O nodes worked....although I've done this as a matter of course when cleaning up the code and my numerous correction action attempts. So I don't have a good feeling the cause has been identified.

I did observe the very bizzare occurance: The FPGA_SOM_Serial.vi had a solid run arrow - Which was impossible...For I loaded the DevKit CLIP and updated the Project...my FPGA_SOM_Serial.vi which had the Tx, Rx I/O nodes - which don't exist in the DevCLIP showed unbroken wires?. So LabVIEW did not detect the invalid node calls....which could indicate it did not detect and propigate the updated CLIP change logic thru the FPGA target vi's?. (My name for the Tx and Rx were 'nTx' and 'nRx' so they did not match the Devkit Serial line node names at all).

I think is would benefit exploring this error, as it's appears to be a random alignment of issues. I'm am concerned it can happen again as the code develops.

Thanks for your support on this...This project is just starting and there is more code to write!

Regards

Jack Hamilton

[tannerite]

Jack,

I took your FPGA_SOM_Serial VI and tried to instantiate the DevKit CLIP but the run arrow always breaks when I change the socketed CLIP in the LabVIEW Project. I am not able to reproduce that particular behavior.

The above removing/re-adding is only a workaround and not the end-all solution for this issue. I completely understand your worry, here. If you could provide the full MAX Technical Support Report from your laptop as well as your recently-imaged machine, that would be helpful in weeding out software discrepencies.

- Tanner

[MrJackHamilton]

Tanner,

I generated a Max report - highlighting my Software Tree...and attached to my original post above. Ni_support2.zip.

Regards

Jack

[Spex]

Hi Jack,

I want to confirm one step in Tanner's instructions, because I also downloaded your code and reproduced your compile error.  I was able to resolve the error by deleting and recreating all of the the "nRS23_Tx_out" IO nodes on the diagram.  Based on your replies, I can't tell for sure if you deleted you IO nodes and recreated them as a test.

Thanks,

spex