Hardware CAN error on 9651

[MMO832]

Hello,

I have an issue on the CAN of the eval board. I have systematically an error message with the code FFFF772D.

I use a NI USB-8473 which work properly on other system; the device (PCA82C251T) on the eval board  seems work properly too (the idle's behaviour) .

So, what's happen? The CAN's pin of the SOM don't work?

regards,

MMO832

[Aix-La-Chapelle]

Hi MMO832,

Have you gone through the CLIP Wizard and enabled the CAN port?  Are you using the example provided with the reference carrier board?  This error may occur when the CAN interface has not been created.  Additionally, I will be filling a corrective action request to get this error to be more descriptive in the future.

Thanks!

Matt

[MMO832]

Hi Matt,

I used the clip (DevKit) provided with the getting started and I tried too use a clip with only the CAN activated.

In the two cases, I have the error message.

Regards,

MMO832

[MMO832]

Hi Matt,

We solve the problem to communicate through CAN.

The VI's CAN run on the RT, and the only way to launch the CAN is to start a FPGA code too.

In fact on our test code you only use a VI on RT however to work properly, I must run a FPGA VI to flash the I/O config. I thinks is an issues for run a code only in RT.

Regards

MMO832

[Eric-M]

Hi MMO832,

All of the peripherals that you can enable in the sbRIO Clip Generator are routed and may have some logic in the FPGA, so in order for the peripheral to function, it is required that this code be compiled and running on the target. If you are not currently doing anything in the FPGA, then the recommended steps are to open up a blank VI, compile it, and deploy it to the SOM as a startup application.

To give a little bit more background, this approach allows for the option to choose how many of the FPGA signals from the high density connector can be used as peripherals vs raw FPGA DIO. We chose this approach becuase you are able to implement only the peripherals and I/O signals required to try and optimize your design as much as possible, which is usually the main goal with using a product like the SOM.

Best,

Eric

[Spex]

Hi MMO832,

This is largely repeat from what Eric mentioned, but I thought I posted this yesterday and an error must have occurred. 

Any peripherals that use FPGA IO must be configured in the CLIP generator, compiled into an FPGA VI bitfile, and the bitfile must be loaded onto the SOM before they can be accessed in RT software.  This is based on the configurable/flexible nature of the Zynq SoC processor at the heart of the SOM.  NI could have elected to hard wire all these peripherals out and include them in the default software, but this would reduce the flexibilty and number of general purpose IO available for customers who don't need all the peripherals.

This requirement is noted in the one page of printed getting-started documentation that is included with the SOM development kit:

The error behavior is expected for the SOM, but I apologize that the explanation of the error is poor and doesn't offer insight into what should be done to correct the problem.

Regards,

spex