sbRIO-9651 Max DIO Speed?

[Spex]

The example you have shown is a way of implementing a serializer/deserializer with discrete logic, but won't be the most efficient way to implement with an FPGA.  If you can compile that example at 240MHz, it may be of use, but I doubt the discrete implementation will get you to the speeds you are looking for.

SERDES blocks are dedicated, configurable blocks within the FPGA SelectIO resource (Xilinx term for an input or output pin and associated logic resources.)  The Xilinx 7 Series SelectIO Resources User Guide (UG471) has more information on the capabiltiles of the SERDES in particular in chapter 3, page 141.

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

These capabilities are an advanced feature of the SelectIO, and require custom VHDL development within the socketed CLIP to enable and to take advantage of SERDES. 

The only NI example of taking advantage of SERDES with socketed CLIP that I'm aware of this this tutorial on modifying one of the FlexRIO Adapter Module CLIPs to change the serialization ratio for different speeds.

https://decibel.ni.com/content/docs/DOC-36140

I have a high-level understanding of the capabilities and benefits of SERDES for FPGA IO, but VHDL and SERDES implementation are outside of my ability.  Hope this helps get you started.  Perhaps others with a history in VHDL based design can offer more assistance.

-spex

[Mrmas]

Hi again,

I will look into SERDES dokumentation from Xilinx.

I was also wondering, does enabling DDR input in the ni 9651 also requiere advanced FPGA knowledge or is it more standard?

Regards

[tannerite]

Enabling DDR requires instantiating VHDL using Xilinx primitives like IDDR/ODDR which is documented in the SelectIO Resource Guide -- this is not configurable in the sbRIO CLIP Generator.

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[Mrmas]

I see.

Is this sort of advanced fpga setup covered in NI fpga training or if i contact NI for application help?

Or is it something i should discuss with a third party with fpga expertise?

Regards

Mas

[tannerite]

Mas,

These advanced FPGA concepts are not covered by NI training as a CLIP is VHDL. If you do not have a background in VHDL I would recommend working with a third-party or someone who is more familiar with creating CLIPs, if a custom CLIP is required. I would recommend working with an Alliance Partner specializing in Electronic Design.

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