5641R FM-Demod Regeneration

[TimS.]

Another question on the DDS. I would like to shift my signal down (to the left) by 2.5 MHz. So, I set the Sine Parameters to 2.5 MHz with an Implementation of LUT = 4096, AmpRes = 16bit, Use top-level clock = 20 MHz, and Output sine and cosine is checked. The help file says that the top-level clock must match otherwise there will be compile errors. However, if my data processing SCTL is running at 50 MHz how do I use the sine wave generator within that loop if it is configured for a 20 MHz clock rate? Every (valid) sample from the FM demod will need to be multiplied by the output of the sine wave generator in order to achieve the shift I want, correct? I'm just unsure how the 2.5 MHz sine/cosine waves will be multiplied with the data in when the phase resolution is from a 20 MHz clock but the express VI is being called at 50MHz. Any advice would be greatly appreciated.

Thank you,

Tim S.

[jaced · Accepted solution]

Hi Tim,

I apologize, but it looks like I was mistaken and the sine wave generator is not supported in a SCTL. I believe this clears up why it is asking to be matched to the top level clock, because that is the clock which it will base its calculations on. I believe the quickest path to a functioning DDS for you is to use the Xilinx core generator and IP integration node which I linked in my last post, there is a tutorial on how to open the core gen and get up and running, We are using a Virtex 5 SX95T, this information is also available in the specifications. I am unsure about the filter issue in your previous post and have passed this question on to the appropriate people.

[TimS.]

Hi JaceD,

I did end up installing the Xilinx CoreGen and building a DDS. I've tried to integrate it into my processing SCTL that's running at 50 MHz but I seem to be missing something. The output data after multiplying the FM demoded data by Sine/Cosine is not valid when writing it to my D/A. It may be hard to develop a picture of what I'm doing but I've attached a snippet of my processing loop as well as a powerpoint that contains screenshots of how my coregen is configured. I took the VHD file and integrated it into the FPGA code using CLIP. Let me know if you have any recommendations on things to try or if you see anything that I'm not doing correctly. Keep in mind I'm still fairly new to FPGA development in terms of thinking about clock cycles, fXP math, etc. I'm learning it all slowly but I think that is my biggest hurdle right now :-).

Thanks,

Tim S.

 

[TimS.]

After re-reading your posts and reading the link on Integrating External IP using the IP Integration Node I realized that you weren't using the CLIP feature and that the IP Integration Node would most likely be closer to what I want to use for incorporating the Xilinx CoreGen files. However, when I tried to install the IP Integration node I can't seem to find it anywhere in my LabVIEW palettes. I've even browsed through the program files folder to see if I could find the IP Integration Wizard anywhere in there but I couldn't. Have you seen this issue before?

The main reason I would like to use the IP Integration node is because it allows the specification of FXP data as inputs and outputs where as the CLIP node only allows signed or unsigned integer values and then I would have to do bit shifting (I think). Also, it seemed like the IP integration node was better for use within the SCTL's and at higher throughputs than the CLIP nodes but I can't really comment on that for sure.

Thanks,

Tim S.

[jaced]

I have not encountered that issue before I have attached an screen shot of my FPGA pallette and the IP intergration node's location. If it is not in the location I suggest posting on the discussion forum for the IP Integration node found here: http://decibel.ni.com/content/thread/3534?tstart=0

[TimS.]

Hmmm, it would seem that the IP integration node is not compatible with the PXIe-5641R FPGA Target. When I go to create an FPGA target using one of the CRIO devices the IP integration node appears on the pallette as it should...

[jaced]

I think this may be an install issue because I am able to see the intergration node when opening a project with the 5641R as the target. Could you try opening the template example and see if it appears on the palette? Attached is a screen shot of the addons palette with the 5640R config loop behind it.Or did I not understand your issue?

[TimS.]

You understood my issue correctly. When I open a project with the 5641R as the target I cannot access the IP Integration node. After opening the 5641R template as you suggested I still cannot access the IP Integration node. However, I did discover that if I open the PCI-5640R template (with the PCI-5640R as the FPGA target) my palette looks identical to yours. So, it appears that I can access the IP Integration node in my palette from any FPGA target except the 5641R.

Here are my software/driver version in case it helps any:

LabVIEW 2009

5640R/5641R driver: 1.4b0

NI-RIO: 3.3

[TimS.]

I figured it out this morning. When using the "edit palette set" advanced option it displayed a message that indicated each FPGA target has it's own palette set menu. So, via the other forum about the IP integration node that you pointed me to I added the vi.lib\rvi\NIPI\xnode\NIPI.xnode to my palette set and now it works. There just must have been something wrong with my PXIe-5641R palette menu when it installed.

Regards,

Tim S.

[TimS.]

Hi JaceD,

I just wanted to let you know that I have successfully integrated the DDS Sine/Cosine generator into my code. I can now frequency shift an incoming IQ signal to the left or right by using the Xilinx IP core and the IP Integration Node. It was much easier to get the code working with the IP Integration node than when I was using CLIP or anything else. Thanks for the help!

-Tim S.