About using FIFO Clear in FPGA Module 5640R

[xy_se]

Hi all,

I am using three target-scoped FIFOs to stream data in my FPGA module, and they are in three paralell while loops(not SCTL).After using them, I wanna clear the FIFO content. According to the help info of FIFO clear function, I put three FIFO clear functions in one flat sequece. But, I am always getting the compilation error saying error code 6, and it is king of saying some synchronization clock signal is used twice(and thus causes the error). I tried to put only one FIFO clear fuction in the flat sequence, it is OK. But I have to clear all my FIFOs, so How to deal with this trouble?

ERROR:HDLParsers:1202 - "C:/NIFPGA85/srvrTmp/LOCALH~1/SU2190~1/rvi_sunny_FPGA_vi_FPGACompileCopy1.vhd" Line 3839. Redeclaration of symbol OClk.
ERROR:HDLParsers:843 - "C:/NIFPGA85/srvrTmp/LOCALH~1/SU2190~1/rvi_sunny_FPGA_vi_FPGACompileCopy1.vhd" Line 19940. Formal OClk of NI_LV_Queue_ACK_F3ED8139500D489 is used twice.
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Total memory usage is 460640 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
 

I attach the screen shot here. 

Thanks!

Sunny

[Andrew_E]

Hi Sunny,

Thanks for the question and sorry that no one has gotten back to you sooner. Try putting the Clears each in a different sequence of the continuous sequence structure. You currently have them all in the same sequence. Just right click the sequence structure and say add frame after . Do this twice. Then place your other two clears in each one of those sequences. That way there will be one clear per frame.