Configuring the IF-RIO's DAC channels

[hanusaem]

We're working on creating a simple fpga project to output a modulated sinusoid, and we're having a little trouble understanding the steps involved in properly configuring/using the DAC channels.  Do you have any resources that explain how to do so?  We've gotten the examples to work on the board, but we've yet to properly run any of our own code that uses the DAC on the FPGA.

Thanks.

[JerryAL]

Hi Evan

It would be a little more helpful if I had more specific information on your project.  For the following, I’m assuming that you are creating IQ data in the FPGA and passing this to the DAC.

Using the DAC requires that the clock for passing data to the DAC and the sample rate at which the DAC are configured correctly.  Ideally, the DAC should run at 200 MSps for best signal performance.  Depending on the amount of interpolation configured, the data should be programmed to go to the DAC at the IQ Sample Rate, which is created in the DAC.

To configure the Clocks, you would use the ni5640R Configure Timebase.vi.  Refer to the Timebase section of the NI 5640R Help file for more information and diagrams.

There are a number of controls on the front panel. 

If you are running the module on the internal clock, it is best to leave the default settings for the Reference, VCXO, CDC Clock Source controls.

The CDC7005:Routing controls will be the ones most commonly used.

Depending on the DAC to be configured, set the Y2 (DAC 0) Division or Y3 (DAC 1) Division control for the amount you want to divide the CDC clock source down by for the DAC sample rate.  Using the 200 MHz internal VCXO, this will provide frequencies of 200 MHZ (/1), 100 MHz (/2), 50 MHz(/4), 25 MHz (/8), and 12.5 MHz (/16).

PLLing

If you are PLLing the module to an external reference clock frequency, select the following settings:

Reference: Select the source of the reference clock frequency with the Reference control, selecting either RTSI Ext Ref Enable or SMB Ext Ref Enable.  RTSI(7) Direction should be set to False if RTSI Ext Ref Enable is configured.
 
VCXO: Configure the VCXO Control for PLL and the VCXO Enable for True.

CDC Clock Source: Should be left to VCXO.

DAC Configuration

To configure the DACs, you would use the ni5640R DAC Configure for Quadrature Mode.vi to configure the DAC. 

There are seven controls.  Refer to Figure 18 of the CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter specification sheet for more information.

The first four controls should be set in most cases.

DAC - Set this to configure the DAC to be used.

Frequency (Hz) - This sets the frequency of the DDS CORE of the DAC.  This will be the IF frequency out of the module. 

Previously Configured REFCLK Freq (Hz) - This is the frequency configured with the ni5640R Configure Timebase.vi.  This is the Sample Clock Rate, the frequency at which the DAC clocks data out.

CIC Interpolation Factor - Sets the amount of interpolation the DAC is to perform on the signal to be generated with the CIC PROGRAMMABLE INTERPOLATOR.  There is a Fixed 4X interpolator in the DAC.  The CIC interpolation factor should be multiplied by 4 to get total interpolation. Divide the Previously Configured REFCLK Freq by the total interpolation to calculate the DAC_<0/1>_IQ_Clk.  The DAC_<0/1>_IQ_Clk is the rate at which the IQ data must be passed to the DAC in a Single Cycle time loop.

The following two controls are optional.

Output Scale Factor [0, 1.99] - This provides a method of scaling the amplitude of the data before the DAC.

REFCLK Multiplier - This configures the DAC to multiply by the set amount, the reference clock frequency, to run the clock.  This would mostly be used if you were using and external clock. For Example, you provide an external 10 MHz clock, and multiply it by 20 to run the DAC at 200 MHz.  Usually you would use a frequency from the CDC clock chip at 200 MSps for best signal performance, and this is not needed.

[Ex-NISH2]

I need some help to understand the DAC IQ Clock.

Let's take the NI 5640R IQ Output example.  Do you mean when I set the CIC interpolation to 50 on the host, the FPGA automatically sets the DAC IQ clock to 2MHz (100MHz/50)?  Is this setting conflict with DAC_?_TxEnable?

[Mauricio Capistran-Garza]

The DAC IQ Clock is equal to the sampling clock divided over the interpolation and then multiplied by 2 (since the IQ data is interleaved). However, you have to remember that there is a fixed 4X interpolation that is not configurable. So, the formula would be like this:

IQ Clk = ( 200 MHz / 4 * CIC interpolation ) * 2.

So, if you select a CIC interpolation of 50 on the host, the IQ Clock ends up being 2 MHz, even when the acutal IQ Rate (the rate at which IQ samples is consumed) is only 1 MHz.

The setting has nothing to do with DAC_n_TxEnable.

- Mauricio

[Ex-NISH2]

I tried to set my 5640R to take external 10MHz ref clock fron the SMB Clock In, but it seams not working. 

1.  Is there any example code?

2. Is there any specifications on the Clock In?  Frequency range? Level?  Is there any VI taking the settings of External Clock Frequency (if my clock is not the default frequency)?

Thanks.

[JerryAL]

Hi Ex-NISH2

1. Setting the module up to use a frequency reference is relatively easy.  On the ni5640R Configure Timebase.vi, the following must be set:

Reference: SMB Ext Ref Enable: True
VCXO: VCXO Control: PLL

The following image shows the block diagram constants for the setting.

2. The specifications for the reference clock in are in the NI PCI-5640R Specifications under the External section.  Repeated below for reference:

External

External sample clock sources:    CLK IN (SMB connector)

External sample clock range:        30 MHz to 200 MHz

External reference clock sources: CLK IN (SMB connector), RTSI

External reference clock range:     1 MHz to 100 MHz in 1 MHz increments, ± 100 ppm (RTSI limited to 20 MHz)

PLL lock time:                                < 250 ms

External clock input amplitude
Sine wave:                                     0.63 Vpk–pk to 2.8 Vpk–pk (0 dBm to 13 dBm)
Square wave:                                 0.25 Vpk–pk to 2.8 Vpk–pk

External clock input impedance:   50 Ω nominal, AC-coupled

Message Edited by Jerry_L on 06-06-2007 12:59 PM

[Mauricio Capistran-Garza]

Hi Ex-NISH2,

Just want to chip in that there was a bug in the 1.0 release that prevented it from working correctly. So please make sure you have the latest version installed (which would be 1.1)

[KIRAN SIDDANADHAM]

Hi,

I have a few queries regarding the DAC IQ CLK

1)Is it possible to set  DAC IQ CLK to 15000 Hz

2)What is minimum value for DAC IQ CLK

        IQ Clk = ( (VCXO/N2) / 4 * CIC interpolation ) * 2.

                  = ((200M/16) /4*63)*2

                  = ((12.5M)/252)*2

                  =  99206

So,minimum possible  DAC IQ CLK is 99206 is it correct     or     there are other parameters that effects DAC IQ CLK to decrease further

[jaced]

Hi, 

Your calculations look correct to me, if the internal clock is used. It is possible to go lower if you provide an external clock, but the lower bound would be dependent on the clock you provide down to the minimum of 1Mhz which gives a min IQ CLK of 7,936 Hz.  You could also use data repetition to achieve a slower effective sample rate. 

[KIRAN SIDDANADHAM]

Hi JaceD,

Thanks for ur reply,

I have one more query,I have taken the the FPGA example "ni5640R Analog Input and Output", in that I have changed the Routing clocks, in that i have specified the Y2 divide by 16(to set DAC IQ CLK to 12.5MHz).There I am getting an error like this

*******************

Error -61046 occurred at ni5640R Analog Input and Output (HOST).vi

Possible reason(s):

LabVIEW FPGA:  An error was detected in the communication between the host computer and the FPGA target.

If you are using any external clocks, make sure they are connected and within the supported specifications. Also, verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support.

 ****************************

I am unable to solve this error,Can u explain this error and how to resolve this error.

Regards,

KIRAN KUMAR S