Confirmation on Clock Generation

[creed]

I would like to run my design at a specific rate (10.762238MHz).  Using the Derived Clock tools,

I can't create a clock at this rate.  Is there any other method I could use to generate the clock

rate I want? 

The only other approach I can think of is to perform a clock recovery function and use an

enable signal to control the dataflow.

Regards,

[jaced]

Hi Creed,

I believe the options you have will depend greatly on what you are trying to accomplish. If 10.762238M is the rate of the data then it may be possible to resample the data to a more manageable rate. As you already mentioned clock recovery is another avenue to explore. Can you please expand a bit on what you are working toward and what this rate is for.

[creed]

I'm looking to implement a 512 tap complex correlator. The signal I'm receiving is an 8vsb signal. If I can fun at the symbol rate (10.762238MHz) I have the option of using a complex filter that runs a a lower rate. If I can't do 10.762238 then I need to run at a higher sampling rate and the filter could be real. In general, it would be nice if the Ni cards supported the different dtv symbol rates (5.056941, 5.360537 and 10.762238MHz)

[jaced]

Hi Creed,

There are two ways I can see to accomplish this, one would be a fractional resampler, which is available in either modulation toolkit if you want to do it on host or the LabVIEW FPGA RF communication Library http://decibel.ni.com/content/docs/DOC-4068 if you wish to perform it on FPGA. You can also use an external clock at that specific rate or multiple thereof.