DAC_0_IQ_CLK

[afd-2000]

Is the default nominal frequency of the DAC0 IQ clock 100 MHz or 50MHz?  Its default value was 50MHz before I updated our software, but it not defaults to 100MHz, and when I compile my FPGA VI, I get a failed compilation report that says that I made a timing violation involving the DAC0 IQ clock.

[Mauricio Capistran-Garza]

The default nominal frequency was changed to 100 MHz because that's the highest frequency at which you can run the IQ Clock. So, compiling at this rate will ensure that you code works in all possible clock configurations. However, if in your application you will be using a slower clock, you can change this paramenter appropriately. You just have to be carefull never to run your design faster than what you specified.

- Mauricio

[afd-2000]

Unfortunately, I receive a failed compilation report due to timing violations while the DAC IQ clock is running at 100 MHz.  This might have been the problem I was getting with my other data, as I configured the clock to run at 100 MHz in the host VI, but had it set to 50 MHz in the FPGA VI.  What sort of measures would ensure that I would not get timing violations, because the compile report only suggests that I "reduce long arithmetic/combinatorial paths" or "use pipelining with timed loops."  I don't see how I could reduce the code I have (besides deleting the DMA FIFO), and I have no idea how to use pipelining with timed loops.  Does anyone have any suggestions on how to fix this problem?

Here is a screenshot of the DAC loop in my FPGA VI.

[JerryAL]

Hi afd-2000

Basically, everything in the loop must run in one clock period, or 10 ns for a 100 MHz clock.  That is pretty fast for they way your VI is written.  Pipelining would come in very handy.

In terms of pipelining, there is a description in the NI 5640R Help file.  I recommend reading it.  It will definitely help your issue.
NI 5640R Help/NI-5640R Programming/Using FPGAs for Signal Processing/Pipelining

You may also want to read the following post for more information:
http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=3

I also suggest that you also refer to the ni5640R IQ Output example that is installed with the ni5640R software.

Jerry

[Mauricio Capistran-Garza]

I think you don't have to run the DAC IQ Clock at 100 MHz. In general you want to use high frequency clocks when you need to generate wide bandwidth signals. If you're generating a sine tone you could run the IQ Clock at a much lower rate, like 1 MHz.