DIO and PSK-ed DAC synchronization

[tigr]

Hi

We somewhat modified "Analog Input and Output - ASYNC" example adding toggling DIO line  

All behavior seems expectable, but there is a problem with alligning DIO pulse (top waveform, 640 nsec duration) with PSK signal's bit border (bottom waveform, carrier freq = 25MHz, bit rate = 1.5625 Msps). Note, that 1.5625Mbps exactly corresponds to 640nsec duration and two waveforms can be alligned. Which synchronization method can be implemented to allign pulse edge with bit border ? 

[Elizabeth_K.]

Hi tigr,

Since you are using the Asynchronous programming palette for IF-RIO, there is no good way to synchronize your DIO to the DAC output. I would suggest moving to programming the FPGA in the non-asynchronous mode, as in this mode the data will follow the data flow programming paradigm, which will allow you more accurately align your DIO to the DAC output. 

Would you be willing to provide more information about the signal you want your DIO to align with? Or perhaps you could attach an example VI?

Regards,

Elizabeth K.

[tigr]

Hi Elizabeth

Just now an idea appeared to put DIO generation blocks into "Proc Data Out" sub-vi. Such way it should be synchronized (alligned) with data bits. Will try and inform later 

tigr