Data interfaced to the PCI-5640R

[bc2007]

I am using the Communications Pioneer Program with the PCI-5640R. I would like to include a bit generator (LabVIEW VI) into one of the examples (ni5640R Input and Output (HOST).vi) that came with the package.

How do I interface the bit generator into the program so that the FPGA receives the data and outputs it on the 70Mhz channel?

Next step would be interfacing user data to the FPGA from the Host PC. How is that interfaced?

Tks much

[Mauricio Capistran-Garza]

Hi,

Could you please elaborate on what you are trying to do?

Not all VIs that are available in LabVIEW for the PC are also available in LabVIEW FPGA, so, you might have to do some development to get some features working in the FPGA. If you are refering to the Modulation Toolkit VI called "MT Bit Generation", that VI can not be deployed to an FPGA. The purpose of that VI is to generate a pseudo random bit sequence, which is typically used as a digital message input to the digital modulation VIs. One alternative is to implement a pseudo-random number generator in the FPGA by using a Linear Feedback Shift Register (LSFR).

- Mauricio

[bc2007]

Mauricio,

Tks for your input. I was trying to use the MT Bit Generator, no wonder it wasn't working. I'll give your suggestion a try.

Jeff

[Mauricio Capistran-Garza]

Hi Jeff,

Could you still elaborate on your application? Even after you have the bit generation ready, you will still need to modulate it somehow before generating it. I just want to make sure you are not missing any major blocks.

- Mauricio

Message Edited by Mauricio Capistran-Garza on 07-02-2007 01:50 PM

[bc2007]

Mauricio,

Are you familiar with the NI Communications System Design Pioneer Program which uses the NI LabVIEW FPGA Module? I am using the PCI-5640R transceiver board, NI Comm. program and its Application Software programs to build a transceiver with an I.F. at 70 Mhz.

Jeff

[Mauricio Capistran-Garza]

Hi Jeff,

I am familiar the the NI Communications System Design Pioneer Program. However, I'm uncertain about the characteristics of the tranceiver that you want to build. For instnace, are you planning on doing modulation and demodulation on the FPGA or in the Host? What type of modulation/demodulation are you doing? What is the expected bandwidth of your signals? Are you doing any pulse shaping filters? If you are doing digital demodulation, are you planning on writing a symbol clock recovery algorithm and a frequency correction algoritm? Do you have a particular protocol in mind? Do you want to the board to "respond' to a given message?

There are just a lot of things involved and it's trivial to implement a full transceiver in the FPGA, that's why I'm asking.

- Mauricio