ERROR:HDLParsers:850

[Ex-NISH2]

I got an error report at the end of compile.  It shows something wrong with a subVI on FPGA target.  Here is the copy of compiler info:

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Compiling vhdl file "E:/NIFPGA80/srvrTmp/LOCALH~1/TRYIFR~3/rvi_visn_FPGA_Detect.vhd" in Library work.
Entity <rvi_visn_FPGA_Detect> compiled.
ERROR:HDLParsers:850 - "E:/NIFPGA80/srvrTmp/LOCALH~1/TRYIFR~3/rvi_visn_FPGA_Detect.vhd" Line 338. Formal port Clk1 does not exist in Component 'SubVICtlOrInd'.
-->

Total memory usage is 183748 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...

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In this subVI, I have one time critical loop using DAC clock, one time critical loop using ADC clock, and another one normal loop.

Is there anyone can help?

[jdigiova]

Can you include your code in this post? I will take a look at it and try and reproduce the error.
Regards,
Joseph D.
LabVIEW FPGA PSE

[1k2k]

I have multiple FIFO write in 2 SCTL, and one of them is in a subVI, so I got strange error report.

I copied the subVI diagram to the main VI, the error message makes more sense, and helped me to find out the FIFO bug.

[jdigiova]

Well I am glad you were able to track the problem down. The writing to the same FIFO from 2 separate places make the FIFO a shared resource and therefore this shared resource must have an arbitor. Any resource that must have an arbitor will not work in a SCTL. The error message you received after moving the diagram from the subVI to the top-level VI hopefully stated some type of invalid abitration on a queue. This error should have come up during the code generation process which proceeds the actual compile process. The first time you ran this code you were getting compile errors during the compile process. We should have caught the invalid arbitration even if the FIFO was in a subVI and thrown a code generation error rather than delaying the error until the compile process. I have not been able to reproduce the compile time error when writing to a FIFO from 2 SCTLs and including one in a subVI. I always get the code generation error. I would like to investigate why we didn't catch the invalid arbitration in your case. Can you send the original code, or a simplified version that exhibits the behavior?
Regards,
Joseph D.
National Instruments