Hi luchingo,
I tried you project and was able to see your error by starting a compile. I have not determined why, but I was able to run a successful compile after deleting both elements on the block diagram (the FPGA I/O Node and the boolean indicator) and then re-creating them.
To place the FPGA I/O node, I dragged it from the project tree (FPGA Target / Digital Line Input and Output / DIO_1) to the block diagram and placed it in the configuration loop. Then I rt. clicked the output terminal and chose 'Create -> Indicator'. I then saved the VI and the project and compiled the FPGA VI. I stopped seeing the error. Could you try this and see if it causes your error to disappear?
Is this how you originally wrote the code (using this exact sequence)? Or did you copy the IO Node from a different VI? Or drop a blank IO Node and then choose the DIO_1 target? Or.. ? [I haven't been able to re-produce your error by starting with an unmodified version of the example.]
On a side-note, I'd recommend you add the RTSI_Ref_Clk to your project (rt. click on 'FPGA Target' and 'Add -> FPGA Base Clock') and create a separate timed loop configured to run on that clock. Then I'd place all of your custom DIO code in that loop and not mix it into the configuration loop. This will let you run your DIO at a different speed without affecting the configuration of the rest of the board.
~Philippe
