FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17

[JerryAL]

Hi PD2

I forgot to add that the filter example I provided requires the Fixed-Point Math Library for LabVIEW FPGA.  This can be downloaded from the following link:
https://lumen.ni.com/nicif/us/nilabsfixpntlib/content.xhtml

Jerry

[pd2]

I made a block which emulates a 1024 element array which can be indexed for a read, but can only be written by writing to the beginning and shifting everything down towards the end. It does not use arrays at all. But I just realized that memory blocks would probably suit my needs better. Have you had any trouble with the compiler and memory blocks?

[pd2]

I just finished writing an FFT block for the FPGA that uses memory blocks instead of arrays. During my first compile attempt, my computer suddenly restarted with a Windows stop error after about twenty minutes to half an hour of compilation. However, the stop error might have been caused by a driver unrelated to LV. My second compile attempt went for about 45 minutes and ended with an error while mapping. I am now trying a third compile attempt.

I am quickly approaching a deadline; so any advice would be greatly appreciated. I'll attach the text of the compile. Let me know if you need to look at the code that was being compiled.

[JerryAL]

Actually, it would be better to see your LV project.

J

[pd2]

I just looked over the error message in more detail. It appears that xst and ngdbuild finish fine, but map fails. Is it possible to run map again without running xst again? I would like to do this because xst typically takes over twenty minutes to finish. Could I use the command line to run some of these commands manually?

Edit: I didn't notice your message before I posted. I'll send you a zip of my project. The host VI might be messed up right now since I'm making a lot of changes to it.

Message Edited by pd2 on 07-15-2008 09:28 PM

[JerryAL]

Sorry, I don't know the answer to that question.  You might have more luck posting that question to the LabVIEW forum with FPGA in the title.  This forum is more to the hardware specifics of the IF-RIO.  General questions on LV FPGA will get more visibility in the LabVIEW forum.  Plus their are a lot more followers of that forum that are experts in LV FPGA. 

My knowledge fall more to the hardware side of the module, and average LV FPGA knowledge.  And at this time, I can't refer this to someone with more knowledge.

J

[pd2]

Ok, I'll post on the main LV forum.

[JerryAL]

You can still post your project (all files), but I probably will not be able to look at until tomorrow.

J

[pd2]

See my new message at http://forums.ni.com/ni/board/message?board.id=170&thread.id=341241 for the project.