FIR filter core within SCTL

[pranavhp]

Hi,

I have generated a xilinx FIR filter core to be able to give one ouput sample per clock cycle.
I am trying to filter incoming I and Q samples in SCTL linked to ADC_0_Port_A_Clk.
Within SCTL, I am using HDL node interface routine to import filter core.
So far I have not seen any success.

There are few issues I still cannot figure out about SCTL.

1. Which clock would the FIR would be using within SCTL? ADC_0_Port_A_Clk or Configuration_Clk?
2. Is there anyway to access ADC_0_Port_A_Clk within SCTL?
3. In this SCTL, what is the relationship between enable_in and ADC_0_Port_A_Clk signals?

Thank you,
PHPATEL.

[Mauricio Capistran-Garza]

1. Which clock would the FIR would be using within SCTL? ADC_0_Port_A_Clk or Configuration_Clk?
It should work on the ADC_0_Port_A_Clk.

3. In this SCTL, what is the relationship between enable_in and ADC_0_Port_A_Clk signals?
When you're on an SCTL your enable_in signal is enabled as long as the loop is active.

- Mauricio

[niggger]

Que onda Mauricio, Hasta que di contigo, soy Edgar del Pierre Faure, espero leas el mensaje, estoy organizando una comida de la generacion de secundaria, yo se que vives fuera y seria complicado que vinieras es el 20 de mayo, de todas maneras pasame todos tus datos a mi correo edgar@ivector.com.mx  para incluirte en el directorio.


Saludos.  tambien agrega tu msn para comunicarnos

[JerryAL]

Hi

I think you posted this to the wrong NI Message board.  This is meant for help with the NI PCI-5640R IF Tranceiver.

If you wish help in another area, I would suggest posting to the Spanish language board:

Discusiones sobre Productos NI

http://forums.ni.com/ni/board?board.id=6170

Have a great day.

Jerry

PS: Mauricio says Hi.