FATAL_ERROR:Xst:....

[aub]

Greetings to all,

Two questions:

1) We were trying to compile an FIR project on the FPGA and we faced several problems. After 15 hours of compilation, the following error was popped out:

FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13.276.1 -

This application has discovered an exceptional condition from which it cannot recover.  Process will terminate. 

ERROR:Xflow - Program xst returned error code 1. Aborting flow execution...

We also noticed the following during compilation: "INFO:Xst:738 - HDL ADVISOR - 640 flip-flops were inferred for signal <out_l>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time"

and we don't know the cause of such problem? Do you have any hints?

2) When creating a real time application between the host VI and the FPGA VI, we put a timed loop on the FPGA VI, and then read the values using the read/write

control function in a while loop on the HOST VI. How can we know how often the host read/write control function reads a value from the FPGA VI.

Does the read/write control function reads a value from the FPGA on every iteration of the FPGA loop? If No, what controls the iteration duration on the HOST VI?

In other words, How does the while loop in the HOST VI synchronize with the FPGA timed loop?

P.S. Putting a timed loop on the HOST VI is not an  option becuase the used dt on the FPGA VI is too small (corresponding to a zero on the HOST)

[JerryAL]

Hi aub

1.  I’m not sure what is causing this error.  15 hours sounds way too long for something to compile, unless you are using a very slow computer.  By any chance are you using creating arrays?  We’ve noticed that the Xilinx compiler can take very long times to compile FPGA code that contain arrays, and this has led to the compiler ending with an error.

2. The two loops you have running, the one on the FPGA and the one on the host computer are running in two separate processes.  There is no inherent function that ensures that every FPGA write to an indicator is guaranteed to be read by the host computer program.  There is no inherent synchronization.

There is also no rule of thumb to determine how many times a loop on the computer may run faster or slower than the FPGA computer.  This is determined by the speed of the loop on the FPGA and how fast the loop reading the value from the FPGA on the host computer is running.  If the host computer loop is running once for every 5 loops of the FPGA loop, 4 samples out of 5 are being lost.  If the host computer loop is running faster, it will read the same value multiple times until the FPGA updates with a new value.

The best method here is to set up DMA FIFO.  Read multiple samples at the host level.  You can set up a loop after the return to process each sample individually if you must.

[aub]

Greetings to all,

Yes we are using arrays with local variables. I guess you are right.

However, in the case of using DMA and local FIFO and upon reading elements from the FIFO, it pops out the oldest element. Is there a way to pop out elements at certain indices from the FIFO; similar to indexing arrays.

Thank you for your time and cooperation,

AUB

[jdigiova]

If you are passing data within the FPGA VI than you can use the Memory functions which do allow indexing. Another option for passing data around on the FPGA (other than FIFOs and memory) would be global variables.  Globals are not as efficient as using block memory, but they are more efficient than local variables because extra logic is not needed to pass data to/from a Host VI because globals do not have front panel objects.

If you  need to get the data to the Host than DMA is the best option.

Regards,

Joseph D.

National Instruments

[manikg]

Hello,

1.

 We are also seeing the following error message:

WARNING:Xst:524 - All outputs of the instance <TimeoutManagerx> of the block <TimeoutManager> are unconnected in block <FifoPopControl>.   This instance will be removed from the design along with all underlying logic
FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13.276.1 -
This application has discovered an exceptional condition from which it cannot recover. 
ERROR:Xflow - Program xst returned error code 1. Aborting flow execution...


"the Xilinx compiler can take very long times to compile FPGA >code that contain arrays, and this has led to the compiler ending with an error."
In our case the compilation ran for 1.5 hours on a Pentium III with 512MB RAM; could this still be the cause ?

2. 

We are using two 16-bit arrays (from a front-panel connector) and four 32-bit arrays (from a global variable). The arrays size is 64 elements.
We do not have 'create arrays' and 'array local variables'.  However, we do have a for loop with replace array subset and I would like to know what kind of overhead that may cause ?

In previous iterations, we had longer compilation times when we were using larger arrays and were passing them between sub-VIs and the process ran out of memory.

3.

We will be modifying the code to indexed memory operations, but would like to understand better the workings of arrays. The overheads to be expected when using arrays seem to be very high from our experience.  Any suggestions on the maximum size after which problems can be expected ? Or best-use practices for array operations would be welcome.


Thanks in advance.

Regards,

Manik

[jdigiova]

1)  I am not sure about the first error.  Do you use an HDL node, and if so can you attach your code?

2) Each object that stores data on an FPGA uses 1 Flip-Flop (FF) per bit.  For instance an I16 uses 16 FFs.  If the largest object on the front panel is greater than 32 bits (like an array or cluster), tha largest object uses 2 FFs per bit. 

Since you have 2 front panel arrays with 64 I16s than one of these arrays will use 2 FFs per bit and the other 1 FF per bit.  These 2 arrays use 3072 FFs.

The 4 global variable arrays have 64 I32s for a total of 2048 bits per array.  Since there is no front panel control these arrays take 1 FF per bit for a total of 4*2048=8192FFs.

Therefore to store the array data alone you need 8192+3072=11264 FFs.  The array operations are generally cheap it is the storing the data that takes up space.

3) You should definately move to using block memory when the data in an array would be greater than 256 bits or about 16*I16s.

[manikg]

Hi,
Thanks for the helpful information on arrays. No, we are not using any HDL interface node.  We are in the process of migrating to memory read/writes.

Thank you.

-Manik