Hello Jorge,
When compiling your LabVIEW FPGA program, we must generate the necessary VHDL code and pass it to the Xilinx compilation tools. These tools take the VHDL and generate a complete hardware description to be loaded onto the chip, and this process can be very memory-intensive.
Depending on the size and complexity of your FPGA program, the Xilinx tools may need to run several optimization routines to fit the program onto the available chip real estate. Each of these optimization passes will take more memory, and can be especially resource intensive if large arrays are used in the FPGA VI, particularly on the front panel. It is not unusual for the Xilinx tools to require upwards of 150 MB of RAM on my machine.
How much memory usage are you seeing on your system, and how much physical RAM do you have? If you are using large arrays on your front panel, consider either using a constant on the block diagram, a look-up table in FPGA memory, or a DMA FIFO to send in the data one chunk at a time from the host instead. (each of these will require progressively less space on the chip, and should be able to compile faster and with less memory).
If I can be of further assistance, please let me know!
(and FYI, this board is only intended for the new IF-RIO boards - you can find the regular LV FPGA forum
here.)
Cheers,
Matt Pollock
National Instruments
