Faster while loop clock

[Ex-NISH2]

I want to fasten the while loop in my process, but it looks FPGA forced all while loop clock to be 20MHz.

I have several DSP process procedures using SCTL and FIFO, so I have to use some while loop with FIFO read / write timeout not to be zero for the process in between 2 SCTLs.  I want to make the while loop faster, so I set the top level clock to be RTSI clock, and the process SCTL to use RTSI clock too.  Then I set RTSI clock to be 50MHz.

The compile report checks for 50MHz speed, and get passed.  However, the ADC and DAC FIFO still got empty / full flags.  By counting the loop time with tick counters, and compare with the ADC DAC clock speeds, I think the RTSI clock is reduced to 20MHz.

Question:  Is this too ridiculous?  Is there a proven way to rais the while loop clock to 40-50MHz?

[Ex-NISH2]

I found the problem: 5640R driver reset every clock to its default speed, not the speed counfigured in project file.  The RTSI clock is forced to 20MHz, my 40MHz configuration in the project is ignored.  The problem is, I can not find a VI to set it back.  So I had to use DAC clock 1.

[Mauricio Capistran-Garza]

The RTSI Clk is configured in the "Configure Timebase" VI. That is usually the first VI after the Open FPGA VI Reference. The RTSI Clk can be configured to run at 200 MHz divided by 1, 2, 4, 8, or 16.