Generate sinus in FPGA

[SimonD]

Hi,

I am trying to generate a sinus at 13,56MHz on a 5641R. I manage to do this on the host, but now I want to create this on the FPGA because after I want to realise some modulation to make RFID. And I need to have all the code in the FPGA.

Does someone have an idea of how i can do this, or an example?

Thank you

[jaced · Accepted solution]

Hi Simon, 

You can either use Xilinx core generator and the IP integration node to create a DDS based waveform or you can create it using LabVIEW FPGA . The LabVIEW FPGA tutorial also explains how to use a LUT containing a sine wave, which if you will only be using a single frequency may be a more simple route to go.  

[SimonD]

Hi,

Thank you for this example.

I look it but it's write  "On an R series board this example will run with the maximum 1 MHz update rate of the analog outputs."

So do you think I can reach 13,56Mhz on my IF RIO? If yes, is there any changes to do on this example?

And you're rigth, if I can make this without the core generator, it will be easier.

Thank you for your time

[jaced]

Sorry for not being more clear. The LabVIEW FPGA example is meant to be more of a guide as to how to accomplish this with IF-RIO, You will need to make a few changes such as running it in a single cycle timed loop rather than using a loop timer and adjusting the inputs accordingly. I see no major issues keeping you from running at your desired rate. Please post back if you run into trouble implementing the code. 

[Lars.B]

I used in my former projects with 5641R successfully the FPGA-sine-function for similar tasks.

But therefore I think you're relation between FPGA-clock and target-frequency is not really good: 2,96...  (no n-times of FPGA-clock).

What kind of modulation do you want to use?

The 5641R is capable to create a sine-tone of itself (when configured as single-frequency).

[SimonD]

Hi,

I want to use amplitude modulation.

I am trying to modulate a signal when it's generate with the sine tone. It's not a problem to create the carrier with the sine tone vi, but I don't know if there is a way to find this signal in the FPGA to change the amplitude or an other way to make the modulation in the FPGA.

[Lars.B]

Hi,

this doesn't sound too complicated - if you have the I/Q-data of the sine on FPGA-level then you can tamper its strength, with a scalar. Result would be an AM-modulated signal.

And... to re-think the first problem: if you want to generate the sine signal on FPGA level, I would use the property of I/Q-modulation, that when you feed I with sine and Q with cos, you will get a single sine signal as result (the resulting mirror side band signal for sine on I will be deleted by the cos-part on Q).

As idea for the targeted 13,56MHz: set center frequency of IFRIO to 15MHz and create a sine and cos (with FXP library) of 1,44 MHz - which is not a problem with 40 MHz. These two signals feed in I and Q (with (-1)*cos)... should result in the wished signal.

Greets,

Lars

[SimonD]

I think it's not really difficult to realize my project, but the RF it's a new world for me and I'm a little lost. 

I'm looking on the different possibility, but I think I will generate the sinus on the host level, and make the AM modulation on the FPGA-level.

Do you think it's possible? If I use the quadrature mode vi, with a 13,56MHz center frequency, and write I/Q data with a lower frequency in the FPGA?

And thank you for your time

[Lars.B]

Hi,

if you can set the IFRIO to such a center frequency (I don't know if it's possible), then it is not needed to generate a signal on Host.

Reason is that your AM-modulation would be then a very easy task: just set Q to always 0 - and modulate with I. Strength of signal will then be a scalar to the value feeded to I.

Just to remember: Mixing I with 1 (constant) and Q with 0 will result in a clean sine signal of set center frequency (here: 13,56MHz).

The value of I-component equals then just with signal strength.

[SimonD]

OK I do this and I give you a feedback.

Thanks