Generating an input signal

[afd-2000]

I have completed the FPGA Module tutorial and I am attempting to generate an input signal, but i really don't understand exactly what is going on in the tutorial.  I have two FPGA I/O nodes in the FPGA VI that are labeled "ADC 0 PORT A_I" and a corresponding one labeled Q as well.  I'm assuming that these generate a sine wave that the tutorial used as the input signal.  I want the input to be a sine wave with noise, and Mauricio suggested using DDS, but I don't know exactly how to add this to the existing FPGA VI that I created in the tutorial.  Can anyone help me out on this one? 

[Mauricio Capistran-Garza]

I'm a bit confused by your post. The FPGA Module tutorial guides you through the creation of a VI that acquires a signal. The I/O nodes labled "ADC 0 Port A I" and "ADC 0 Port A Q" are the I and Q elements of the acquired and downconverted signal. Just to be able to test this code, the HOST VI also configures one of the Analog Output channles in "Single Tone Mode" and therfore generates a sine through it. However, the FPGA is not doing anything to generate the sine tone, it's the DAC which is configured to generate the sine tone.

The I/O nodes that you need to use to generate signals are the "DAC 0 Data" and "DAC 0 TxEnabled". You will also need to use another clock, the "DAC 0 IQ Clk".You might want to read some documentation on the Analog Output and look at the IQ Output example. You can find the documentation on this post: http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=140

[afd-2000]

alright mauricio, i have the DAC_0_data and the DAC_0_txenable I/O nodes set up, and a true/false control is wired to the DAC_0_Txenable.  i'm not too sure what the Txenable is doing, but i think i can find out.  My issue is with the generation of the sine wave using DDS.  So the sine look-up tables and phase accumulator should generate an output that goes to the DAC_0_data block, which can be read in the Host VI.  There is an input to the DDS that concerns me though, called "Message," that apparently contains the frequency that the sine wave will be generated at.  I'm not sure what sort of signal this would be, or how to generate it in the timed loop that I created that runs on a DAC_0_IQ clock.  What sort of signal should this "message" be?  I'm sorry if it seems like i am posting too frequently, but i'm learning a lot about the IF-RIO and things are becoming much clearer than they were.  So thanks a lot for your help

[Mauricio Capistran-Garza]

The screenshots that I sent you were for doing FM Modulation, that's why the control was called "message". In your case, this will be a constant value, usually called "frequency tuning word" or "phase increment", which determines the frequency of the sine. You can find more info about DDS here: http://en.wikipedia.org/wiki/Direct_Digital_Synthesis. One last comment, the DAC takes in interleaved I and Q values, which means that in the first clock cycle (the one in which you assert TxEnable) you must provide the DAC Data with the first I value, the next clock cycle with the Q, the next with the second I, and so forth.