Help with "DAC Configure for Quadrature Mode.vi" in "ni5640R Frequency Translation" Example

[antonio.matar]

Hi there:
I am also using the the NI PCI-5640R and I've been "studying" the program: "Frequency Translation", my intention is to modify it and produce a  closed-loop between I and O. 
I am also interested in transferring what i am reading through the input port, directly to the output port but filtered AND with a phase-shift (final Objective: Q-Control). 
I need to visualize the signal in the HOST, so I need both FIFOS (DMA FIFO and  Local FIFO), and the "Quadrature Mode DAC Configure"

I would like to know:
1. How can I directly transfer the data acquired through the ADC port into the DAC?  (it is unclear due to the Event structure in the "Frequency Translation" example)
2. How can I configure the "Quadrature Mode DAC Configure.vi" for it to bandpass-filter the signal comming from the ADC at a given frequency and BW, specified by the user in the HOST? I have read that it is possible to filter a signal comming to the DAC using DUCs (Digital Upconverters) Does anyone has more info about this topic?
3. Is it possible to configure the "Quadrature Mode DAC Configure.vi" to produce a phase-shifted signal (phase shift also specified by user in the host)

I've been working for almost 2 months trying to program the 5640R, doing examples, and modifying them.  After playing with different examples I've come up to the conclusion that the "Frequency Translation" example is the one that best-suites my application.  My problem now is that I AM LOST because i need more information regarding the configuration parameters of ALL the different VI's inside the NI-5640R VI Tree  to exploit them correctly, specially the "Quadrature Mode DAC Configure.vi".

Can anyone please help me?
Cheers...Antonio

[JerryAL]

Hi Antonio

1. I’m not sure about your comment about the Event structure in the Frequency Translation example.  There is no event structure in the “ni5640R Frequency Translation (FPGA).vi”.  There are two Single Cycle Timed Loops (SCTL), one clocked by the ADC0 clock, and one by the DAC0 clock.  The data is passed through a FIFO from the ADC clock domain to the DAC clock domain.

I also refer you to Mauricio’s previous post on 06-28-2007 08:46 AM above.

2. The DDCs in the DACs cannot be configured for custom filters.   A digital filter will have to be created in line between the ADC port and the DAC port.  Referring to the Frequency Translation example, it can be placed in a third SCTL which can be clocked at a much higher sample clock rate than the ADC and DAC clock rates.  This allows you to have process intensive functions processed in a higher clock domain and maintain your ADC and DAC IQ rates.

3. Do mean shifting the phase of the DAC’s NCO on the fly?

For more information on the ni5640R DAC Configure for Quadrature Mode.vi.  You can look at this forum topic:
http://forums.ni.com/ni/board/message?board.id=ifrio&thread.id=3

Also, the controls for the VIs have been designed to use the same terms whenever possible that are used in the specification sheets for the DAC (and ADC) parts.  You can find more information there.

Jerry

[philippe_w]

Antonio,

The Frequency Translation example is already transferring the data acquired through the ADC port into the DAC. This is done *on* the FPGA itself and the code is in the 'ni5640R Frequency Translation (FPGA).vi' which you can find by looking at the project tree and expanding expanding the FPGA Target node. Note that making changes to the FPGA VI will require you to re-compile the target code. I would suggest you read 'Getting Started with the NI 5640R and the LabVIEW FPGA Module' for instructions on the process.

If you wish to add more functionality to the example, you should add your signal processing on the FPGA side. The HOST side VI (containing the event structure, etc.) only serves to control the target and display the incoming data. On the FPGA side, you can create a separate SCTL (Single Cycle Timed Loop) and a new Local FIFO. Then, you can use one of the Local FIFO's to pass the data from the (existing) acquisition loop to your (new) processing loop, change the signal as you'd like, and pass the data to the (existing) generation loop using the other (new) Local FIFO.

~Philippe

[antonio.matar]

Hi guys, thank you for your quick reply, I'll follow your recommendations and write soon an update!

[antonio.matar]

Hello again:

Jerry:
1. I referred to the Event structure, but in the HOST, but now, with your commentary and Philippe's explanation i've undestood better the concept.

2. Regarding the filtering, I read the datasheet of the AD6654 (DAC from "Analog Devices" which is part of the n5640r) and in pages 36 and 37, it explains with an example, the possibility of designing a Bandpass CIC Filter by changing the interpolation (or decimation) factor of the DUC (or DDC).  The filter can't be fully customized (the rejection and passband are limited to an "Alias rejection Table" in page 36), but it could fit the application to filter certain frequencies.

I also tryed what you guys suggested, meaning: I designed a simple digital bandpass butterworth IIR filter in the FPGA target inside a 3rd SCTL with a faster clock (i.e. "Top level timing source") and using a 2nd Local FIFO.  The filter was done with FPGA discrete delays (z^-n) departing from a "differences equation" [y(n) = x(n-1)+x(n)+0.9996858*y(n-1)].  But I have problems with the 0.99... constant which is always rounded to 1 (check the pic).  I changed the variable's type and digits of precision, but it still rounds up to 1 Any suggestions?

3. I was thinking as well of shifting the phase (as Jerry said) by configurating the NCO in the DAC.  Again, more information is given in AD6654's datasheet  (page 35).  I will quote the info:

"The phase offset register can be written with a value that is added as an offset to the phase accumulator of the NCO.  This 16 bit register is interpreted as 16-bit unregistered integer.  A 0x0000 in this register corresponds to a 0 radian offset and a 0xFFF corresponds to an offset of 2pi*(1 -  1/2^16) radians.  This register allows multiple NCOs (multiple channels) to be sinchronized to produce complex sinusoids with a known steady phase difference:"

Any ideas of how to program this register inside the "ni5640r ADC Configure NCO" to have a fixed phase offset of 90º?

Thanx in advance for your replies
'till the next post...Antonio

[antonio.matar]

Sorry I uploaded the wrong picture, here the Local FIFOS are correctly ordered!

[JerryAL]

Hi Antonio

1. Sorry, I thought you were referring to the LV FPGA code in terms of direct connection between the ADC and DAC ports.

You’re correct about the specifications.  I usually frame my answers in terms of the features that are designed to be supported by their released software.  I’m not an expert on going down to that level.  Although, if you look at the ni5640R FPGA host VIs, you can drill down into the VIs to see the actual register level call that are made to configure the DAC.  This code also goes through the configuration loop in the LV FPGA diagram.  This can be modified to add features that the hardware is capable of, but unfortunately, while many of these extra features may work, they are not tested.  And also outside my range of expertise.

2. I have two comments about your filter.  You are filtering the U32 data type which contains both the I and Q components.  But it is still a U32 number.  You must split the I and Q out to I16 values and filter each component in parallel with two separate filters. 

In terms of the 0.999 value not being able to be realized with an integer value, there isn’t much that can be done.  If you want to use a decimal number that small, the only way to do it is to shift the data to a higher “precision” integer data type.  Either I32, or more likely I64.  If you are using LabVIEW 8.5, it now supports an integer data type where you can 20 bits for your calculations if you want.  I believe that you can go all the way up to 64 bits.

Jerry

[JerryAL]

Hi Antonio

Sorry, I was thinking about your previous post and realized I may have missed your point concerning this line:
“But I have problems with the 0.99... constant which is always rounded to 1 (check the pic).  I changed the variable's type and digits of precision, but it still rounds up to 1 Any suggestions?”

I’m not sure you realize that all floating pint numbers must be rescaled to do integer computation on the FPGA.  You can’t just a take a number of floating point filter coefficients that range from -1.0 and 1.0 and expect to use them directly on the FPGA.  The numbers must be converted to an integer before sending down to the FPGA.

For example. You have a set of number ranging from -1.0 to 1.0.  Depending on the resolution you require, you can either use an I16 or and I32 data type.  Using I16 data. One way of do this is to equate 1.0 with 16384 or 32767.  There are two ways of looking at this.  If you choose 16384, you can convert a floating point values up to 2. Actually 1.999938964844, if 16384 = 1.0000, then the largest I16 positive value (32767) will equal 1.999938964844.  On the other hand, 16384 is 100000000000000 in binary.  This means that when scaling a value by one, you do not change the actual binary representation of the number.  The benefit of using 32767 is that you gain an extra bit of resolution in your number if you are only concerned with floating point values between -1.0 and +1.0.

You can also find more information on scaling here:
http://zone.ni.com/devzone/cda/tut/p/id/3661

Jerry

[antonio.matar]

Hi Jerry:

Thank you for all the useful information regarding the constants. At this moment I am more focused in the Phase Offset problem inside the NCO.
I've been trying to modifying the registers of the ADC and I found useful information provided by Mauricio, in the "PSK Reciever" thread from the IF-RIO Message Board:
http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=439&query.id=37696#M439.

But haven't been succesful to modify the "Frequency Translation" program to succesfully aqcuire a sinusoid and generate the same signal, with the same frequency, but variable phase offset.  It seems to be a little bit complicated to do all this signal manipulation in the FPGA Target. 

I thought of several ways to generate a phase shift in the FPGA Target.  We've already discussed the first one (programming (somehow) the registers in the NCO from the ADC).  Some other ways I thought could be possible are:
(1) introduce a "wait" or discrete delays
(2) introduce a digital word with a known length (comming directly out of the FIFO) inside a 1D array and rotate the data.

The only problem implementing this solutions is that the "offset degree" can't be introduced by the user.  Any tips of how to do this (the phase shift) in the HOST?

[antonio.matar]

Hi:

I've been able to modify the registers in the ADC to have a variable NCO phase offset.  Thank you for all the info and all your replies!
Right now i am focused in modifying the program to have a variable gain, by adding a control to the "Output Scale Factor" pin.

I've had some problems with the last objective, they are reported in another post:
http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=638&query.id=119999#M638

Any suggestions are welcome!