Help with timing report

[--thatguy]

I'm trying to compile my SCTL to run at 240MHz.

Typically when I do compiles at these rates I can stumble through my timing report, locate the longest path, and add feedback nodes.  I do this iteratively until I can meet the requested timing.

However today I've come across a timing report I can't interpret.  Up until this last report there was mention of my SCTL by name.  Now it seems to be in code I didn't write. 

Can someone please explain

=========================================================================

Timing constraint: Default period analysis for Clock 'SysClkIn40'

Clock period: 24.843ns (frequency: 40.253MHz)

Total number of paths / destination ports: 689990 / 15142

-------------------------------------------------------------------------

Delay: 4.140ns (Levels of Logic = 3)

Source: myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1FromInterface/HBx/oDlyPushToggleChanged_0 (FF)

Destination: myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1ToInterface/HBx/iLclStoredData_0 (FF)

Source Clock: SysClkIn40 rising 6.0X

Destination Clock: SysClkIn40 rising 6.0X

Data Path: myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1FromInterface/HBx/oDlyPushToggleChanged_0 to myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1ToInterface/HBx/iLclStoredData_0

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FD:C->Q 17 0.471 1.157 myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1FromInterface/HBx/oDlyPushToggleChanged_0 (myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1FromInterface/HBx/oDlyPushToggleChanged_0)

LUT6:I0->O 1 0.094 1.069 myWindow/theVI/n_747/Clk40Derived6x1DataValid_SW0 (N2581)

LUT6:I0->O 2 0.094 0.485 myWindow/theVI/n_747/Clk40Derived6x1DataValid (myWindow/theVI/n_747/Clk40Derived6x1DataValid)

LUT2:I1->O 33 0.094 0.463 myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1ToInterface/HBx/iLclStoredData_and00011 (myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1ToInterface/HBx/iLclStoredData_and0001)

FDE:CE 0.213 myWindow/theVI/n_747/Clk40Derived6x1Crossing.Clk40Derived6x1ToInterface/HBx/iLclStoredData_0

----------------------------------------

Total 4.140ns (0.966ns logic, 3.174ns route)

(23.3% logic, 76.7% route)

=========================================================================

Let me know if I need to include any other info (screen caps, full compile reports, etc.)

[Sappster]

Hi That guy,

I'd like to investigate this error closer. Can you attach the contents of you compilation folder here? The folder can be found within this directory:

C:\NIFPGA86\srvrTmp\localhost\

There should be a foldernamed after your project located there. If you can zip the entire contents of that folder I will take a look at them. It would also be helpful if you could attach a screenshot of your single cycle loop.

[--thatguy]

Mark, 

I've included the screen cap in the zip file.

Thanks for taking a look into this. 

[Sappster]

Hi thatguy,

It looks like the issue revolves around  the FXP sin/cosine function. I'd like to know what the properties are configured to. Please send a screenshot or explination. Have you beenable to successfully compile previously using that function?

Thanks,

[--thatguy]

Mark,

I've been able to compile previously at 40MHz.

I've attached screen captures of the configuration screens for the function.

In the interim I'll look into creating my own version of the function to see if I can't get it to run faster.