Internal clock rate

[Roman Gassmann]

Hi,

in my work with the NI5641-R I need to implement an IIR filter in a Single cycle loop with a clock rate of 25MHz. Since a serial implementation lead to timing violations (it is obviously clear, that the serial calculation time will exceed the 40ns) I successfully implemented the filter in a parallel manner. Thats where I realized, the FPGA is able to process roughly 15 multiplications per cycle. This lead to the question of the core clock of the FPGA. In the documentation it is stated that the internal clock rate is 200MHz. But then just 200MHz / 25MHz = 8 cycles will result. By the assumation that an single multiplaction is done in 1 cycle this lead to 8 multiplications, which obviously is not the case. Researches in the Virtex-5 documentations resulted in the fact that the core speed of the FPGA is 550MHz, which with the same assumation lead to 22 multiplications.

Thus, my questions now are: what core clock rate has the Virtex-5 of the NI5641-R and how many multiplications are possible in a single cycle loop with a clock rate of 25MHz.

Thanks

Roman Gassmann

[jaced]

Hi Roman,

I believe the confusion comes from taking a processor like approach to this issue. The FPGA does not have a single core clock which all operations are performed on but one can think of it as travel time through logic. With this in mind we can say a multiplication takes x amount of time and the routing for this logic will take y. So the total time taken for the entire step is obviously x+y+ propagation delays etc, If you are running your single cycle timed loop(sctl) at 25MHz, one cycle is going to take 40ns. There are other factors which will come into play such as a setup/hold time reducing this to something less than 40ns. The thought behind the sctl is that everything inside will execute or if we use our example travel through the logic within the allotted amount of time. The time that each block takes varies based on its architecture and routing needs. With all of this being said I cannot give explicit answers to your questions because there are many variables with will come into play. I do suggest that one can use pipelining to allow the loop to iterate which will in turn allow the FPGA to perform operations which may take longer than one clock cycle to complete. More information on pipelining can be found here:

http://zone.ni.com/reference/en-XX/help/371576C-01/5640r/def_pipelining/

http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgaconcepts/fpga_pipelining/