Is there a common(or systematic) way of have IQ data interleaved and sent? (PCI 5640R)

[david uang]

Hi,

    Thanks for the help!
   I have a further question about the IQ data.
   I am trying to write my baseband output to the DAC_IQ channel. I have two questions:
   1. what is the representation of IQ interleaved data? I mean, how they are interleaved? What data type should I use to write to the DAC_IQ? I see in one of the example that the data is contained in a I16, then processed with x2^(-2). Does that mean the -32576/4, 32576/4 is actual the range of the input to the DAC_IQ?

   2. Is there a usual way of interleaving the IQ data? (In the FPGA rather than in the host). I saw how they use array to interleave the data in the host block diagram.

   Thanks a log.

David
  

[JerryAL]

Hi David

1.  The representation of each I and Q sample is I16.  But the data must be in the lower 14 bits for the 14 bit DACs.  So, looking at an I16 number, the actual decimal data range will be from -8192 to +8192.

They are interleaved I and Q, over and over.  This is so that the I is the first data point out of the FIFO for the DAC, which requires the I before the Q for every IQ pair.  There is an example of this in the ni5640R IQ Output example.  Actually a subVI of the host VI.

2. I’m not sure how to answer this one.  It sort of depends on where the samples are coming from and how they are created / stored.  In the same IQ Output example, the data is interleaved by reading each I or Q value out of a FIFO at a time.  In the ni5640R Frequency Translation (FPGA).vi, the data is saved in a FIFO as U32, combining both the I and Q sample.  When retrieved from the FIFO, the U32 sample is retrieved every other iteration of the loop.  The data is split, and the Q is shifted to the next iteration to write to the DAC, preserving the order that I and Q samples must be written to the DAC.

Jerry

[david uang]

Thank you Jerry!

  I have another question, is the output range of ADC the same? What is the mapping relationship between the integer number of ADC output / DAC input and the actual voltage?

Dayu

 

[JerryAL]

Hi David

From the NI 5640R specifications document:

Full-scale input range: +8.5 dBm peak   (1.68 Vpk-pk sine) at 10 MHz (± 0.5 dB max calibration data uncertainty; <± 1 dB typical without calibration)

Full-scale output range: +2 dBm peak (0.8 Vpk-pk) nominal into 50 Ω,  –1.5 dBm with sinc and total interpolation factor = 4 at 10 MHz  (± 0.5 dB max calibration data uncertainty, <± 1 dB typical without calibration)*

Jerry