clock of PCI 5640R

[david uang]

Hi!

   I got a little bit confused by the clock of PCI 5640R.
   What does "nominal frequency" which appears when I add a clock in in the Project Explorer mean?
   How does it come into play with the following equation?
   DAC_<i>_IQ_Clk = 2 × REFCLK_{DAC_<i>} × Clock multiplier_{DAC_<i>} / Interpolation_{DAC_<i>}
  
   Thanks!

Dayu

[JerryAL]

Hi Dayu

The "nominal frequency" field in the Project Explorer is basically a value that the Xilinx tools use to determine if the FPGA code will run on the FPGA.  In the process of compiling the code, it will determine the maximum speeds that portions of the circuit will run at.  Say you specific 75.0 MHz.  If Xilinx thinks the circuit can run at 100 MHz, there are no problems, but if Xilinx thinks that the circuit’s maximum speed is ~70 MHz, it will fail.

You should only have to change this if your FPGA code can’t run at the default number and you want to clock the circuit at a much slower rate.  Then put in a value higher than the rate you are going to clock it, and lower than what the Xilinx tools say is the maximum rate for your code.

This value does not really factor into the DAC_<i>_IQ_Clk equation, which is configured with the Clock and DAC configuration VIs.

Jerry