Missing Samples from FIFO

[pranavhp]

Hi,

I am trying to move data from SCTL(lower clock domain) to "while" loop (higher clock domain).

I have attached schematic of a VI.

To test the logic I am writing a ramp value to local FIFO in SCTL and then I am reading value in while loop.
After which, I am writing a read value into a DMA FIFO.

I have attached ramp values that I collected on PC side.

This implementation is not only loosing samples but it is writing data value twice.

I cannot figure out why this happens.  I hope someone would comment on it.

Thank you,
P. Patel.

[Mauricio Capistran-Garza]

Hello,

I'm not sure what is happening, but I have some ideas about it. First, I noticed that you are not checking the "Full" flag on the "ADCTemp" FIFO. My guess is that you are actually trying to write data faster than you are reading it. That would explain why you see it skip some values; when you write data to a Full FIFO then the data is dropped. Even if the while loop where you are reading the data is running on a faster clock, you have to take into account that since it's not a single-cycle loop, all the process is done sequencially, so you may very well be reading the data slower than you think.

The second problem that you describe (getting repeated values) might not really be a problem. I'm guessing you are using double precision representation for that data. If that is the case, LabVIEW only displays 6 digits of precision by default. So that would mean that the values that you are seeing twice are actullay different values, which differ on the last digit, but it can't be seen displaying only 6 digits of precison. To fix that, right-click on the control and choose "properties" and increase the digits of precision.


I hope this helps

- Mauricio

[pranavhp]

Hi Mauricio,

You are right. The local FIFO is showing full flag.
I think I assumed "while" loop's datapath would be much faster than SCTL's one.

Could you or someone else give me a suggestion about correctly exchanging data between these two loops?
I tried using following Occurrence concept but I could not compile the design:
You cannot use the Wait on Occurrence function in a single-cycle Timed Loop. However, you can use the Set Occurrence function. You then can use the Wait on Occurrence function outside the single-cycle Timed Loop in a While Loop or For Loop.

I want create a  VI to receive sample from ADC at slower clock loop and process it in higher clock loop.

Thank you,
Pranav.

[Ex-NISH2]

Make the DA loop faster than the AD one.  Or set the FIFO big enough (bigger than the max ADC length).

You need to check the FIFO empty flag in the read FIFO side.  And it looks like you get the FIFO empty flag when you read the last element, so you need some logic to detect whether the FIFO read gives you a valid data.