ONE MORE TRY

[crio]

HI ,

I HAVE ATTACHED MY FPGA VI PROGRAM IN THIS POST......i understand that the output apperars at the AOx port from there i am using a high rate data cable (high freq) to obtain the signall  output on to the osciloscope..... i jus wanna know why am i not getting the waveform output when i am using that program.

hope my program explains my problem

thank you

valli

[JerryAL]

Hi Valli

I'll look at this as soon as I can, but if the issue is not seeing data on a oscilloscope, have you tried running the shipping examples?  They should give you an output that you should be able to see on your scope.  If you do not see any thing on your scope with the example, it may be an issue other than your code.

J

[Christian_L]

Hello Valli,

Based on just the VI that you attached to your question, as long as the Phase Increment nd Phase Offset controls have a value of 0, the output of the Sine Generator will also be 0 and you will have a steady voltage on the output of the DAC.

Try setting the Phase Increment to a value like 100 or even 1000. This should generate a sinewave on the output. The phase increment allows you to programmatically set the frequency of the sinewave. If you remove the Phase Increment and Offset controls, the sine generator will use the settings specified in its configuration dialog.

[JerryAL]

Hi Valli

In addition, the NI 5640R’s DACs are designed to only accept waveform IQ data.  This is done serially.  I, then Q, I, Q, etc.  Every time your loop runs in your VI, the sine generator gives you the next value of the sine wave.  The problem is that the DAC is taking one sample as I, and then the next sample as Q, and so on.  This data is used to “modulate” the data when upconverted to the configured carrier.  I’m not sure what you are sending the DAC will look like at the output.

You really do need to look at the NI 5640R Examples to get started and look over the NI 5640R Help file to get started.  The ni5640R Frequency Translation and ni5640R Input and Output examples would be a good place to start.

I get the impression that you think that passing a sine waveform, sample by sample, to the DAC will get you a sine wave out of the DAC.  You will, but that is the carrier created by the DAC’s NCO.  The amplitude and phase of the carrier will depend on the IQ signals you send to the DAC.

You also need to place the DACx I/O Node in a Single Cycle timed loop to ensure that you pass data from the FPGA to the DAC at the correct time for each sample.

Jerry

PS: Can you reply in the same message thread instead of creating a new one for every reply?  It makes it easier for people to follow the discussion.  Thanks J.