PSK receiver

[tigr]

hi all

We are trying to alter DDC phase shift on the fly for PSK receiver. Straightforward approach (phase offset register -> freq. hold-off counter -> Hop Soft/Pin Sync) seems not working. Is somebody experienced in such activity?

Thanks

[Mauricio Capistran-Garza]

Hi

Ok, the reason why the phase offset is not working is because you have not specified which DDC channel you are writing to. You should write the Channel IO Access Control Register (0x02) to enable the first DDC Channel, then write the phase offset and then do a Soft Sync. I'm attaching a screenshot of the modified version of your VI that does such thing. I've tested this approach and works fine.

- Mauricio

[tigr]

Mauricio

Thank you for the advise. Now I have a somewhat more difficult question. All we are doing takes place within HOST vi. This seems inacceptable for real time system. The question is how to adjust NCO phase offset within FPGA TARGET vi ?

Fist, we should measure instataneous I and Q, and then calculate arctan(Q/I) within FPGA vi. All this is not a problem. The problem is when we try to increase/decrease in the same SCTL the NCO phase by the value previously calculated (FPGA-based PLL). Do you have any idea concerning the interface to NCO control registers within FPGA vi ? May be via direct microport R/W ?

Thank you in advance

[Mauricio Capistran-Garza]

Hi,

Configuring the ADC real-time is not a straight forward procedure, but it's certainly possible. Let me try to explain how the configuration usually happens. The ADC is configured through an interface called the Microport (you can find the datasheet in here: http://www.analog.com/en/prod/0,2877,AD6654,00.html). I highly recommend looking at the datasheet to understand the entire functioning of the microport, but this is a summary. The microport has 7 signals: CPUCLK, RD, WR, CS, A, D, and RDY. It is throgh this lines that you can read and write registers. All these lines are exposed in the FPGA as I/O Nodes, so you can definitely access them directly from the FPGA. However, in order to minimize logic in the FPGA the code for reading and writing the registers is written in host VIs. The microport I/O nodes are wired directly to controls and indicators (in the Configuration Loop) such that are accessible from the host.
So, the good news is that all the logic to interface to these signals is already writen. The bad news is that it's all in host VIs, so you will need to do 2 things:
1) Take those VIs and make them FPGA compatible. This means deleting the error in / error out clusters, changing any floating point data to integer / fixed point, make sure you don't dynamically allocate any arrays. Find the VI named "ni5640R ADC read_write (multi-bite).vi" that's the top level VI that contains all the logic you are looking for.
2) You might still want to do some of the configuration through the host, so you will need to create some arbitration to prevent both the FPGA and the host to try to access the port at the same time.

- Mauricio