RTSI at 80 MHz

[luchigno]

Hi

I'm using a NI5640R board. Is it possible to set the RTSI clock at 80 Mhz in the Host vi changing in some way the Configuration timebase vi?

With this vi I can set the RTSI clock at 200 100 50 25 12.5 MHz but 100 is to high for the FPGA vi (the maximun when compiled is 95 MHz)  and 50 is too low for what I need to do. I tried to pipeline the FPGA but there were no significant results.

Thanks in advance for your help.

Emanuele

[JerryAL]

Hi Emanuele

Sorry, it is not possible to set the RTSI clock to 80 MHz when using the 200 MHz internal timebase.

If you were to use an external timebase of another frequency, you could get other frequencies based on the divide down values.

Is the part of your code that you need to run faster than 50 MHz in a single cycle timed loop?  It may be that the part of the code that is making the XILINX tools calculate the maximum frequency of 95 MHz is something other than the part you wan to run faster.

Jerry

[luchigno]

Hi Jerry,

Thanks a lot for your help.

First of all I can't use an external clock.

Yes the part of the code is inside a SCTL at RTSI clock= 100MHz.

Anyway.. you are right...I used the RTSI clock=100MHz as top level clock and there is a while loop (at which rate does it run?) that should generate a Timing violation (if it runs at RTSI clock). Now I change the Top level clock (I replaced the RTSI with Configuration clock=20MHz) and it works.

Thanks

Best regards

Emanuele

[JerryAL]

Hi Emanuele

With respect to which rate the while loops runs, that depends on what it in the loop.  When code is placed in a normal while loop, most of the functions placed in the loop have extra FPGA logic associated with it to control timing. Depending on how long the pipeline is to finish the logic in the loop determines how long it takes for each iteration.

You can place a Tick Count VI in your loop and a shift register.  Subtract the difference between successive iterations of the loop, and pass the values up to the Host VI with a FIFO to see long each iteration takes.

Jerry

[david uang]

Hi Jerry,

   May I insert one question? It seems from the reply that in PCI5640R, the normal while loop is not usually runned at 20MHz. The Labview will calcuate how long it takes for one loop to finish and generate a clock to drive the while lopp. Am I right? If there is parallel multiple normal while loops, the Labview will generate a clock for each loop?
  Thanks.

David

[JerryAL]

Hi David

If your code is not in a single cycle times loop, or in the normal while loop, all the code will be clocked at the 20 MHz rate, but that does not mean that the full chain of code will complete in one clock cycle.  In these case most LabVIEW functions will take a number of clock cycles to completes it function.  Then the data is passed onto the next function, and so on until the end of the chain of functions.  Then the loop starts from the beginning again.  A loop will have a loop rate determined by the total length of pipeline delays from each function in the chain.

Here is a link that discusses optimize loops for LV FPGAs.

http://zone.ni.com/devzone/cda/tut/p/id/3749

Jerry