Sample Clock for the ADC AD6654 on NI5640

[xdumoulin]

Hi,

I'd like to sample a signal with a NI5640 card. It's a RF signal of 20MHz. I use the ADC 0 Port A Clk to acquire my samples.

The problem is that this clock can't be up to 25MHz, and this is insufficient for my 20MHz signal. Is it possible to increase the frequency of this clock ? Or can I use another clock ?

I think there is a solution because the sample rate for this ADC is 100MS/s, but I can't find it.

Can you help me please ?

Thanks a lot

Xavier

[Mauricio Capistran-Garza]

Hi Xavier,

The inputs are sampled at 100 MHz. However, the digital signal coming out of the converters goes through a Digital Downconverter (DDC), which brings the signal to baseband. Once in baseband, you only need 25 MS/s to get 20 MHz bandwidth. In the documentation there are brief explanations about how the input and the DDC work. You can read that as a starting point. Also, there is a step by step procedure (in the getting started guide) to build an application that acquires a signal. That should also help you figure out how the hardware should be configured.

- Mauricio

[xdumoulin]

Hi Mauricio,

In fact, the problem is that 20MHz is not the bandwidth of my signal, but my center frequency. So, 25MS/s are not enough, that's why I'd wish to have a bigger sample clock.

I can sample my signal if I'm using the "ni5640R ADC configure NCO" VI, but my signal is already a frequency transposed signal (as you can see on my attachment file), and if it is possible, I would like to avoid to have another frequency transposition.

Can I do my sampling directly without using the NCO ?

Thanks

Xavier

[Mauricio Capistran-Garza]

Hi Xavier,

The DDC in the board can not be bypassed. The samping rate that is used is 100 MHz, so it shouldn't have any problems with your signal which is at 20 MHz. However, once it is sampled, it will get downconverted again to be centered around zero hertz. Could you explain to me why you don't want the signal to be downcovnverted from 20 MHz to DC? Maybe it would be beneficial to understand your application.

- Mauricio

[xdumoulin]

I have a signal GPS of 1.5GHz who is downconverted a first time in 20.46MHz by a RF stage and with a bandwidth of 40MHz (not 10MHz as I said you previously). That's why I prefer not perform a second donwconverting.

I want to acquire this signal to perform processing signal  on it (This is another part. Me, I just have to acquire the signal and convert it.).

We say to me that it was maybe possible to put the 2 ADCs together to increase the sampling rate (if it possible, I have absolutly no idea of the method). Can you tell me more about that please ?

I hope my explanations are clear.

Thanks a lot

Xavier

[Mauricio Capistran-Garza]

Hi Xavier,

Unfortunately, as I mentioned before, there is no way to bypass the DDC in that board, so the board will always downconvert the signal again. Now, using both inputs and getting them synchronized is not trivial, moreover, if you want to do signal processing on the data in the FPGA then getting two streams of data won't work. From that perspective, it looks to me like the 5640R is not the right board for your application. You might want to consider using one of our scopes to sample the signal, such as the 5142. However, I have to ask, are you sure the signal is 40 MHz wide? If I recall correctly GPS signals less than a couple MHz wide.

- Mauricio

[xdumoulin]

Hi Mauricio,

Finally, I will certainly downconcert my signal one more time. As you said it to me, GPS signal is not 40MHz wide, but only a few MHz (I saw some GPS signals downconvert to 3MHz). So, I will try this operation using the DDC and I will inform you of the issue.

Thanks a lot for your support

Xavier