The Dreaded Xilinx Fatal Error

[Mr._Jim]

Hi All,

I've got a PXI-7813R and several C series modules.

When I added some code to retreived LSB weights and offsets, after a while I started getting a compile error repeatedly, and I haven't found a way past it yet.  I saw several posts regarding different fatal errors, but so far I haven't been able to figure out what I've done to make the FPGA gods angry.

Here's the important part of the error message:

Mapping all equations...
FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17 - This application has discovered an exceptional condition from which
it cannot recover.  Process will terminate. For more information on this error, please consult the Answers Database or open a
WebCase with this project attached at http://www.xilinx.com/support.
ERROR:Xflow - Program xst returned error code 1. Aborting flow execution...

Would someone be kind enough to point me in the right direction?  In the meantime, I'm backtracking and attempting to isolate the issue.

Thanks,

Jim

[Bassett_Hound]

Hi Jim,

Check out the following KnowledgeBase:

Compile Failure Port_Main.h:127:1.16 or Port_Main.h.127:1:17

Regards,

Bassett

[Mr._Jim]

Thanks once again, Basset Hound. 

I had tried the instructions in that document the other day without success, but it worked today.  I think I'd made a silly syntactical error before like forgetting the semicolon.  For anyone else who comes across "Port_Main.h:127:1.17", here are the exact modifications I made to vhdl_area.opt, literally spelled out:

...
#
# Global Synthesis Options
#
"-keep_hierarchy SOFT";           # Fix outlined in the NI document           
"-ifn <synthdesign>";             # Input/Project File Name
...

That was very helpful, and all seems to be well for now (fingers crossed).  Now I can get back to concentrating on the problem from my last thread. 

Cheers,

Jim

[Mr._Jim]

Whoops... I guess I posted to the wrong forum.  Sorry about that.

[pd2]

I want to try this, but I cannot find vhdl_area.opt. Where is this file located?

[pd2]

Never mind. I found it. For anybody else with this problem, I found it at "C:\NIFPGA85\Xilinx\virtex\data"

[philippe_w]

Also note that individual targets may override the defaults with a file of the same name in the Targets tree:
"C:\Program Files\National Instruments\LabVIEW 8.5\Targets\NI\FPGA\...\vhdl_area.opt"