Very Very Strange Problem regarding 5640R Compilation,Help needed!

[xy_se]

Hi all,

I encountered a very very strange problem when using FPGA module to compile my design. Originally, I only use one output and one input channel of 5640R, and hook it to a 5600/5610 RF front end to build my tranceiver system. It works fine. But now, I bought another 5600/5610 RF front end from NI. and hooked the output of the new 5600 downconverter to the second AI input  channel to my 5640R. (i.e. two antenna connected to the same 5640R using the two AI inputs). 

Originally, I use one SCTL driven by the ADC_0 clock. Now I have to add another Timed Loop driven by the ADC_1 clock. I did so, and try to compile my new design. 

BUT when the compilation goes to the PAR part(after NGDBUILD DONE), It reports the following error:

 ERROR:  Portability:3 - This Xilinx application has run out of memory or has
   encountered a memory conflict.  Current memory usage is 2090020 kb.  Memory
   problems may require a simple increase in available system memory, or
   possibly a fix to the software or a special workaround.  To troubleshoot or
   remedy the problem, first:  Try increasing your system's RAM.  Alternatively,
   you may try increasing your system's virtual memory or swap space.  If this
   does not fix the problem, please try the following:  Search the Answers
   Database at support.xilinx.com to locate information on this error message.
   If neither of the above resources produces an available solution, please use
   Web Support to open a case with Xilinx Technical Support off of
   support.xilinx.com.  As it is likely that this may be an unforeseen problem,
   please be prepared to submit relevant design files if necessary.

ERROR:  Par:73 - Cannot find Input file "toplevel_gen_map.ncd".  Please verify that your paths and permissions are
   properly set for this file.
ERROR:  Xflow - Program par returned error code 21. Aborting flow execution...

I did search the NI and Xilinx web, and found it is because of not enough memory, and the solution is to upgrade the RAM or increase the virtual memory. My PC is 1GB RAM, so I simply increase my Vvirtual memory to 4GB.It should work, but it failed again.

So I am very confused: my design is so simple, only two SCTLs for the  two AI inputs and one SCTL for the AO.It should not require so much memory!!And my original design with only one AI and one AO, which also includes much more priocessing logics did pass the compilation.Why didn't this much smaller design failed?

Can anyone help me?

Thank you!!!!

Sunny 

帖子被xy_se在 12-11-2008 11:08 AM

时编辑过了

帖子被xy_se在 12-11-2008 11:09 AM

时编辑过了

[xy_se]

Attached is the project.

[xy_se]

I updated my project and locate the problem.But I don't know how to solve it.

I checked the FPGA code, and try to locate the problem. Inside the FPGA code, there are four SCTLs. One is driven by RTSI_REF clock to read data from the Host PC, One is to transmit the data using one AO, the last two are for the AIs. At first, I leave the two SCTLs for AIs and remove the other two SCTLs, inside those two SCTLs I set up two FIFO(target to host) using two different DMA channels. It compiles fine. And then I Add the SCTL for reading data from host, and set up another host to target FIFO inside. The problem occurs. So now it is clear that the possible reason is because of the FIFO. Maybe there exist DMA channel conflicts.

Forget about the previous attached file, please see this one. 

[JerryAL]

Hi xy_se

Your two FIFOs are asking for too much memory space on the FPGA.  Each FIFO is configured for 32,767 U32s and you are using both for a total of 65534 U32s, or 262,136 total bytes.

From the specifications, the FPGA used on the NI 5640R has 2,448 Kbits of block ram available.
( 2448 x 1032 ) / 8 bits = 315,792 bytes.

The XILINX compiler is timing out from lack of memory on your computer because it is trying to make your design work, even though this is an impossibility.

Even though you have 4 GBytes of RAM on your computer, I believe that there is a Windows limitation on how large a memory allocation it will allow, and by default this is 2 GBytes.

Jerry

[xy_se]

Thank you very much,Jerry. I changed it and try to compile again. The limitation is 2GB, i modified it to 3GB by change the windows bootloader.