Hi,
The ADC's max sampling rate (which is the default configuration) is 100 MHz and the DDC inside the ADC supports a minimun decimation of 4, which makes the highest possible IQ Clock to be 25 MHz. On the DAC's, their sample rate is 200 MHz and similarly, the DUC inside the DAC supports a minimum interpolation of 4, which makes the highest possible IQ Clock to be 50 MHz. However, for the DAC, IQ data must be written interleaved in time, which means that you need 2 clock cycles to write a single IQ sample, and that is why the max rate is 100 MHz instead of 50 MHz. Finally, the RTSI clock comes directly from the onboard 200 MHz VCXO. You can configure it through the "ni5640R Configure TImebase VI" to divide it down by 1, 2, 4, 8 or 16 resulting in rates of 200 MHz, 100 MHz, 50 MHz, 25 MHz and 12.5 MHz respectively.
Now, notice that what you specify in the dialog for the base clocks does not configure the clocks to run at the specified rate. The values that you specify in the dialogs are used to create timing constraints for your FPGA code. So, what that means, is that you ensure that your design will run up to the specified clock rate (but it will also run at slower rates).
The actual configuration of the clocks is done though the use of the following host VIs:
1) ni5640R Configure Timebase. To configure the divisor for the RTSI Clk
2) ni5640R ADC Configure DDC. To configure the decimation for the ADC (The clock will be 100 MHz divided by the decimation)
3) ni5640R DAC Configure for Quadrature Mode. Allows you to configure the CIC interpolation. (The clock will be 200 MHz divided by 2 times the configured CIC interpolation)
- Mauricio
