ni 5640R drivers

[lathi]

Hi Sir,
I am vasu.I have started working on your  NI-5640R(version 1.1) LabVIEW card with LabVIEW 8.2.
i have some doubts on this card.
i seen in C:\Program Files\National Instruments\LabVIEW 8.2\examples\instr\ni5640R\Driver four VIs.
how can use these VIs.By using "Stream from Disk" VI i can get(i'll give sine .dat file) sinewave from card DAC output.
By using "Stream to Disk"VI can i get waveform what i given as input to the card.

tell me how can use these VIs for  my requirement( i have to generate QPSK and GMSK signals).


regards
B.Vasu.

[lathi]

Hi
This is Vasu.i am using labview 8.2 n 5640r  card version 1.1.
i am generating modulated signals.for that i am using ni 5640r analog input and output example project.
but i am getting so many errors.
i am attaching my file and error image.
please go through this attachment and tell me solution for eliminating this errors.

Thank you
B.Vasu

[lathi]

Hi
This is Vasu.i am using labview 8.2 n 5640r  card version 1.1.
i am generating modulated signals.for that i am using ni 5640r analog input and output example project.
but i am getting so many errors.
i am attaching my file and error image.
please go through this attachment and tell me solution for eliminating this errors.
Please send me this example project files.i think i did a small mistake.i modified some files in example project it self.


Thank you
B.Vasu

[JerryAL]

Hi Vasu

There were two issues to get the VI to remove the broken run arrow in the host VI.

The first issue is that the ni5640R DAC Enum.ctl and the ni5640R ADC Enum.ctl controls were somehow replaced with the ni5640R FPGA VI Reference.ctl control.  So there was a mismatch in the data type.  I’m not sure how this could have happened. 

When creating a new project from one of the existing shipping examples, the instructions for “Using the ni5640R Template” in the “Getting Started with the NI PCI-5640R IF Transceiver and the LabVIEW FPGA Module”.  Even though it describes starting from the Template project, the steps apply to starting from one of the other examples as well.

The second issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control.  This is an option on the popup menu when clicking on the Open FPGA VI Reference VI.  In some cases, it may already be selected in the popup menu.  In this case, unselect the Bind to Typedef option.  For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option.  In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI.  In some cases, I have to Save All, close the host VI and all subVIs.  Then reopen the host VI.  This has always working in all cases for me. 

If you still have an issue, it is probably another issue than what I saw in these VIs.

Jerry

[lathi]

Hi Jerry Sir

i used what u sent(test_exmp_v02.zip),now i am able to run with errors.

i used this one for my application.but i am getting phase changes.
if i am use low sampling at that time i am not getting any phase changes,
if i am using high sampling rates i am getting some phase changes.
my colleague srinivasulu, e is allready touch with you.
he is also phasing same problem,but he is using ni 5640r IQ output example.


Here i am sending that files.please go through that files.
tell me how i can eliminate that phase changes.
one more if i kept AO center frequency some value i am not getting exact output.i am getting signal with that frequency.but i have to
with my own signal frequency.if i kept zero i am getting correctly.tell me reason.

Thank you sir
vasu

[lathi]

Hi Jerry,
one more doubt.if i am generating more then 15000 samples i am unable to get continous signal.if less then 15000 i am able to get.

Tell how many maximum samples i can generate.

thank you sir
vasu

[JerryAL]

Hi Vasu

If you look at the project, you will see a folder under FPGA Target labeled Memory Blocks. In this folder is the one memory block in the project named AO Memory.  If you look in the FPGA VI, you will see that the samples you are writing to the module are stored in the AO Memory block.

If you look at the properties for AO memory from the project, you will see that it is configured for a maximum of 20,000 samples of U32.  In the FPGA VI, each U32 sample is comprised of one I and Q sample pair. 

If you download more samples than the AO Memory hold, you lose waveform data which will give you a phase discontinuity.

There appears to be an indicator for AO.Memory full in the FPGA VI, but unfortunately, it doesn’t seem to be read in the Host VI to indicate that samples have been lost.  You may want to read this flag immediately after writing data and using this to create an error condition that stops your program.

I’m not sure why the limit is 15,000 samples though….

Jerry

[lathi]

Hi Jerry sir,
Thanking you sir for your information.

You are correct.becaz of AO memory and DMA FIFO depth limited it is not talking more then 10000(both I+Q) smaples.
i changed AO memory size, eventho phase changes are accured.If i fix some lengths like 500,750,15000 Etc i am not getting any phase changes.this is for sinewave.for modulated signal it is not working even i fixed phase changes are accured.
i am not getting exact reason sir.tell me sir can i use any filters to eliminate pahses.it is possible tell me how?

Please spend time for me sir


vasu

[lathi]

Hi sir,

I observed one thing sir.If it is simple sine wave,we can adjust that lengths.if u adjust the length properly (fm*(No.samples/FS)- should be constant integer.) we can get signal with out phase changes.
exp-if i kept length 7500,10000,15000 etc i am able get signal correctly.

My application is modulated signal.i am unable adjust that length because signal length depends upon data,baud rate and Fs.i am unable to get equation like this-fm*(No.samples/FS).
even though i am adjust lengths like 7500,15000 i am not getting modulated signal without phase changes.

now i am able to get simple sine wave,i am not getting modulated wave.i am checking signal in CRO.

Transmit Frequency i kept zero because all ready i up converted my signal in generation itself.


Vasu

[JerryAL]

Hi Vasu

Can you explain what you are seeing a little more specifically in terms of phase change?

From your description using the example, your waveform has a size smaller than the maximum configured size of the memory in the example.  In this case, the waveform should just loop on itself, from your last sample to the first sample, without any phase change.  In this case I am assuming that looping on your waveform is phase continuous.

Do you believe your issue is due to a part of your waveform being lost?  The previous issue, described as a phase change issue, is actually a waveform size issue, or an incomplete waveform being generated.

Jerry