How is the WE* pin on the NAT9914 connected to a Coldfire processor?

[rich59]

I'm designing with a NAT9914 GPIB IC and a MCF5307 Coldfire processor.  How is the WE* pin connected to the Coldfire?

Thanx.

[Collin M]

I'm not familiar with the Coldfire processor. The 9914 has a generic bus interface that should be able to be connected directly to most processors. The CE* pin indicates to the 9914 when a particular transaction on the bus is intended for the 9914. This is needed because there may be more than one device connected to the processor's bus. Whenever the CE* pin is low the NAT9914 decodes the address lines, WE*, and DBIN. CE* must be driven low during any register read or write to the 9914. If CE* is not low the 9914 will ignore the address, WE*, and DBIN pins.

[rich59]

I have a R/W* pin on the Coldfire processor.  The datasheet for the NAT9914 seems to indicate that on the NAT9914 you can tie the WE* pin and DBIN piin together.  Is that true?
Thanx.

[Collin M]

Internally, the 9914 asynchronously decodes register accesses. All of the setup and hold times in the datasheet are referenced to whichever of CE*/WE*/DBIN occurs first or last, respectively.

As long as you meet all the setup and hold requirements you can tie WE* and DBIN together.

Do you plan on using DMA in this application? If so you need to consider the ACCGR* signal also.