How to measure the frequency of a clock using counter in LabVIEW?

[RedAG]

Hi guys,

Anyone know how to measure the frequency of a signal fed into LabVIEW (using the FPGA in PXI-7813R), by using a counter in LabVIEW? 

Essentially, I want to use this counter as a sort of Logic Analyzer.

Thanks, Anoop

[crossrulz]

I would compute it in the FPGA (count clock cycles between rising edges).  I guess you could do this in Windows too.  But that would require sampling the clock and counting samples between rising edges and multiplying by the sample rate.  Again, it would be easier to do in the FPGA.

[RedAG]

Thanks for the reply crosrulz.

how to you count the clock cycles between rising/falling edges? Do you mean manually counting them over a cycle (which has to be identified first) or by using some sort of tool in LV, which would calculate the frequency?

[crossrulz]

Like I said, this is easier in the FPGA.  Want you need to do is use a Single Cycle Timed Loop.  In the loop, read your clock as a digital input.  If it transitions from FALSE to TRUE reset the cycle count (stored in a shift register).  The next time you have a F->T transition, send the count up to the host.  The frequency will be the count divided by the FPGA clock (should be 40MHz).  As far as I know, there is not a built in function to do this, but it is simple enough to code up.

[RedAG]

"If it transitions from FALSE to TRUE reset the cycle count (stored in a shift register).  The next time you have a F->T transition, send the count up to the host"

When you say the above, do you mean, do you mean i have to reset the cycle count when there is a transition?

On a seperate note, do you know why most digital lines float high even when there aren't any input connected to them?

[crossrulz]

---

@The_Sugarman wrote:

"If it transitions from FALSE to TRUE reset the cycle count (stored in a shift register).  The next time you have a F->T transition, send the count up to the host"

When you say the above, do you mean, do you mean i have to reset the cycle count when there is a transition?

On a seperate note, do you know why most digital lines float high even when there aren't any input connected to them?

---

Yes, when you have a certain transition (completed clock), reset the counter (so you start counting the number of FPGA clock cycles until the sampled clock completes a period).

Many DIO have weak pull-up resistors built into the card.  So when left to float, they go high.

[RedAG]

The resetting have to be manual right? If so, this would lead to inaccuracies wouldn't it?

[crossrulz · Accepted solution]

I'm not sure what you mean by "manual".  It is all handled in a case structure.

[RedAG]

Ah ok. But what would I have in the Host to read/display the data obtained from FPGA? A loop and a display?

Also, is it possible to incorporate this code into an existing code (a serial combination of vi's as ooposed to a vi within a vi)?

[crossrulz]

---

@The_Sugarman wrote:

Ah ok. But what would I have in the Host to read/display the data obtained from FPGA? A loop and a display?

Also, is it possible to incorporate this code into an existing code (a serial combination of vi's as ooposed to a vi within a vi)?

---

I would use a DMA to send the data to the host.  The host can then just read the DMA.  You will likely get a lot of readings unless you have an enable/disable transfer setup (another command to send to the FPGA to start/stop sending the counts).  If you get a lot of samples, perform an average.  You then take the count and divide by the 40MHz to get your clock frequency.

You can put this FPGA code wherever you want.