NAT9914 Power On / Reset Sequence

[sreynard]

A few questions on the NAT9914.

What is the NAT9914 minimum or maximum reset pulse width?  How long should the reset line be asserted after Vcc comes up? 

Since I am seeing reverse current out the Vcc when the 9914 control lines are high while Vcc is low, I am pulling the CE, WE, DBIN, and RESET lines low when Vcc is off.  How long do these control lines need to be high before reset is removed? 

[Collin M]

There is no maximum pulse width for the RESET* pin on the 9914. RESET* just resets most of the internal registers when asserted, so it doesn't need to be asserted for very long after VCC comes up. I don't have an exact number for the minimum but a few microseconds should be sufficient. Typically there is some sort of power monitor circuit that will keep a reset asserted for several milliseconds or longer after VCC is stable.

There is also no spec for the control lines being correctly driven prior to RESET* unasserting but the minimum required time is very short.

As for the reverse current, is the device connected to the 9914 driving the interface signals to the 9914 when the 9914 is not powered? Driving signals to the 9914 while it is not powered may cause damage. If the device connected to the 9914 is powered on before the 9914, is it possible to tri-state the control signals and place pullups/pulldowns to the same power rail that powers the 9914?