TNT4882 Register access inconsistency

[Sysol]

We have successfully used the TNT4882A devices on a product designed several years ago. This operates in generic, Turbo-7210 mode. We are now developing a new instrument but even though the design is almost identical we are finding we cannot write and read to the ADR register (07H written/Read to offset OCH). This works fine on the earlier product but even with the same software does not work on the new one. If however the mode is changed to one chip mode (Write 01H to HSSEL at offset 0DH) then the register can be written and read with no problem on both. We have compared the signals on the microcontroller interfaces and the only significant difference is that the address lines settle at the same time as the falling edge of the CSN
line on the new design but 100nS earlier on the previous one. In both cases the timings are well within those required by the specification. (Read/write cycle times of around 800nS). The RDY1 and CPUACC lines are asserted at the times one would expect. Any suggestions please.

[AaronK]

Hi,

The TNT4882-AQ and TNT488-BQ should be identical with regards to reading/writing the ADR.

So the difference between the working and non-working design is when the address lines settle relative to CSN. In the failing case, the address lines settle right when CSN asserts and in the passing case they settle 100ns before CSN asserts. This is allowed by the TNT4882, but usually CSN and RDN are asserted by the host at the same time. The address must be setup at least 24ns before RDN. So if you are asserting CSN and RDN at the same time, you may be violating the timing spec.

Also, verify that you are not in the page-in state. The page-in state is entered by writing 0x50 to the AUXMR.

Hope this helps out!

Best Regards,
Aaron K.
Application Engineer
Nati
onal Instruments