tnt 5002 interface

[theotigan]

After the Findlstn the value of BSR and DSR are

BSR=0x5C

DSR=0xAE

ADSR=0x40

When i read the status of Gpib lines (on dos) whit iblines , i have 0x30, why ADRS is 0x40 and ISR2 is 0x00??

Also the value of the constant pon is 0x00, i already check more dan one time the  register addresses in my sfr5002.h(register addresses file ) i thing all the addresses are true, i wrote it me same..

Here  are the most important Reg addresses ....

#define IMR0 0x1D

#define ISR0 0x1D

#define IMR1 0x02

#define ISR1 0x02

#define IMR2 0x04

#define ISR2 0x04

#define IMR3 0x12

#define ISR3 0x1A

#define CMDR 0x1C

#define SPMR 0x06

#define AUXMR 0x0A

   #define pon 0x00

   #define HLDI 0x51

#define ADMR 0x08

#define ADR0 0x0C

#define ADR1 0x0C

#define ADSR 0x08

#define KEYREG 0x17

#define HIER 0x13

[Collin M]

The BSR register being 0x5C indicates DAV, NRFD, EOI, and SRQ are asserted. The DSR register being 0xAE means that byte is currently being sourced. This indicates there is an active talker sourcing the byte 0xAE and also that SRQ is asserted. Does this make any sense? Are there any other devices connected to this GPIB? What is was the host software doing when you read DSR and BSR.

When you say you read the status of the GPIB signals with iblines was that at the same time you read the BSR and DSR?

It may be that some register accesses are happening incorrectly.

It makes sense to read 0x40 from the ADSR. That indicates everything is in the default state and ATN is not asserted.

Do you have a copy of the schematic that shows the host connection to the TNT5002? Can you verify you are meeting the setup/hold timing requirements of the TNT5002?

Also, I am still suspicious that register accesses are not always happening correctly. Immediately after power-on can you read every register from 0x00 to 0x1F, and then read the same registers after doing the FindLst?

[theotigan]

 

No, there are no devices connect to the Gpib_pci board , i read the Signals status after

Reading BSR and DSR

I thing that the register access work properly , I have tested all read Only  Reg whit default value

Like CNT0…3, CSR etc.. and I always  have the correct value, I also tested Somme Command register like AUXMR and CMDR

like  this test

WriteGpib(0x1E, IMR3);  //  i write IMR3=0x1E

WriteGpib(0x0F, SPMR); // i write 0F to SPMR

ReadGpiB(IMR3);            // I read 0x1E

ReadGpib(SPSR);                   //I read 0F

WriteGpib(0x02, AUXMR);// Reset chip

ReadGpib(IMR3);    // i read 0x00 // Reset Chip  hast clear the value in IMR3

ReadGpib(SPSR);   // I read  0x00  Reset Chip hast clear the value in SPMR

I thing everything work correctly

Look at my code(First post), what can I change for example, maybe I have something Wrong or forget ..

How the TNT5002 recognise that she is addressed? he compare automaticaly the value in ADR0 whit the address from bus or shoul I make it self whit the software ?

 I connect the tnt 5002 whit a µC(renesas M30245) the µC work in Single Chip mode hier are the code that

use to read and write in the tnt register(next post )

[theotigan]

here are the code

// Read Gpib reg

char ReadGpib(char Reg)
{
    char DataRec;
    int i=0;
    //Init Port
    pd2 = 0xFF;       //p2  and p3 direction Output, Adress and Select line)
    pd3 = 0xFF;
    p2  = 0x00;
    p3_0  = 1;
    p3_1  = 1;
    p3_2  = 1;
    p3_3  = 1; 
   
    pd1 = 0x00;       //p1 and p0 direction Intput (Databus line)
    pd0 = 0x00;
    p0 = 0;       
    p1 = 0;
                  
    while(i<2)        
     {          
                               
        //Read Data
        p3_2 = 1;         // Write select signal unassert (sicherung)      
        p3_0 = 0;         //Chip select signal assert                    
        p3_1 = 0;         //Read select signal assert                                
        p2 = Reg;         //Register address to p2
        p3_3 = 1;         //byte reg Access                                     
        Wait(1);          // Delay (1ms).....    
        DataRec = p0;     //P0 = RegData...
                 
        p3_1 = 1;         //Read select signal unassert                        
        p3_0 = 1;         // Chip select signal unasserted                         
        ++i;              
     }                                                   
        return DataRec;
   
}

// Write to tnt 5002 Reg

void WriteGpib(char GpibData, char Reg)     //void  WriteTNTreg(char Reg, char GpibData)
{      
        int i=0;
        //Init Port
        pd2 = 0xFF;           //p2 and p3 direction output, adress and Chip select lines
        pd3 = 0xFF;
        p3 = 0xFF;
        p2 = 0;           

        pd1 = 0xFF;           //p1 and p0 direction output, Data line
        pd0 = 0xFF;
        p0 = 0;       
        p1 = 0;
       
        while(i<2)
         {
            // Write Data         
            p3_0 = 0;         //Chip select signal assert
            p3_2 = 0;         //Write signal assert 
            p2 = Reg;         //Register address to p2 
            p3_3 = 1;         //Byte reg Access            
            p0 =GpibData;     //Data to p0 (D0-D7)low   
            Wait(1);          //Delay(1ms)

            p3_0 = 1;         // Chip select signal unasserted      
            p3_2 = 1;         // Write select signal unassert
            ++i;          
         }
        
}

[Collin M]

I have some comments about your read routine.

1. It appears you first assert CS, then RD, then drive a valid address. The address should not be changed while RD is asserted. You should change this to first assert CS, then drive the address, then assert RD. The signal HWORD should be treated as an address line and not be changed while RD is asserted.

2. You wait 1ms for data to become valid for a register read. Data should be valid 4 clock cycles after RD is asserted. With a 40MHz clock this is about 100ns. So your register read routine takes 1000 times longer than necessary. This may become significant for some GPIB operations. For example, when doing a GPIB read from the host there is usually a timeout at the host. If you have lots of register reads that 1ms delay adds up quickly. By the way, what is the clock frequency for the TNT5002? Is there a way to implement the 4 clock cycle delay without waiting 1 ms?

3. For each call to ReadGpib you seem to read the actual register more than once. Is there a reason for this? Reads do have side-effects for some registers. For example, reading the FIFO moves the FIFO pointer, and reading an ISR can clear an interrupt.

4. I see your read routing unasserts the WR signal. Hopefully this is not necessary as the WR signal should never be asserted when you enter your read routine.

Write routine comments:

1. Similar to read routing comments. You should write the data, address, and HWORD prior to asserting WR. Once the TNT detects RD or WR asserted it latches the address. If the address changes after RD or WR is asserted the results will be inpredicatable.

2. Same comment about 1ms delay and doing each write more than once.


In summary I am not confident that register accesses are reliable. One easy way to check this is to read the BSR when the GPIB is in an idle state, and do an iblines at the host. If these two do not match than something is likely wrong with register accesses.

If the TNT5002 is correctly configured it should respond to its address automatically in hardware. The host detects listeners by sending a GPIB listen address and then examining the state of the NDAC line. If there is a listener then NDAC will be asserted. The TNT5002 will automatically assert NDAC after being addressed to listen.

Also, can you confirm the TNT5002 accepts GPIB command bytes, such as addressing commands, from the host?

  

[theotigan]

 

 The Board steel not reconize my tnt5002 interface

I have change the Read and write Code( next post), i reduce the wait time  to 1µs (the minimum wait time ist 0,1µs)and make some test like

read(CNT0)

read(CNT1)

read(CNT2)

read(CNT3)

I read the correct Reset value, I write and i read the correct value, i tested all the read only reg. whit default value whit success except STS2  at address 0x1C i read 9F instead of 0x0A 

I always tested some AUXMR Command like Reset_Chip (0x02) and it work correctly..

My Board type is PCI-GPIB (488 2) , maybe i must make some extra configuration before i try to communicate whit the tnt 5002 interface??

I alwas do this test.....

Read(BSR) = 0x04

findlstn

Read(BSR) = 0x5C

and

Read(BSR) = 0x04

ibln pad sad alos  pad = 7 and sad =0

Read(BSR) = 0x0C

and

iblines (in dos) Whidout connected the tnt 5002 interface

i have                                           EOI ATN SRQ REN IFC NFRD NDAC DAV

                                                      0       0      0       1      0      0          1       0

Read(BSR) =  0x00 normal.. ->   EOI ATN SRQ REN IFC NFRD NDAC DAV

                                                        0       0      0       0      0      0         0       0

i connect the tnt 5002 interface and i have

Read(BSR) =  0x04                     EOI ATN SRQ REN IFC NFRD NDAC DAV

                                                       0       0      1       0      0      0         0       0

 and iblines (in dos) Whit the tnt 5002 interface connected

   i have                                       EOI ATN SRQ REN IFC NFRD NDAC DAV

                                                     0       0     1       1      0      1          0       0

My DACK# pin is connected  to V++ can't er cause probleme?  i whill not use DMA transfert

Thanks........

 

[theotigan]

Read and write Code

// read code

char ReadGpib(char Reg)
{
    char DataRec;
  
    //Init Port
    pd2 = 0xFF;       //p2  and p3 direction Output,(Adress and Select line)
    pd3 = 0xFF;
    p2  = 0x00;
    p3  = 0xFF;
      
    pd1 = 0x00;       //p1 and p0 direction Intput (Data line)
    pd0 = 0x00;
    p0 = 0;       
    p1 = 0;
                                                           
        //Read Data       //p3_3 = 1 ->byte reg Access 
        p3_0 = 0;         //Chip select signal assert                    
        p2 = Reg;         //Register address to p2
        p3_1 = 0;         //Read select signal assert                                                                           
        Delay(1);         // Delay (1µs).....    
        DataRec = p0;     // Data hold,  P0 = RegData...
                 
        p3_1 = 1;         //Read select signal unassert                        
        p3_0 = 1;         // Chip select signal unasserted                         
                                                                    
        return DataRec;  
}

// write code

void WriteGpib(char GpibData, char Reg)     //void  WriteTNTreg(char Reg, char GpibData)
{      
      
     //Init Port
     pd2 = 0xFF;           //p2 and p3 direction output, adress and Chip select lines
     pd3 = 0xFF;
     p3 = 0xFF;
     p2 = 0;           

     pd1 = 0xFF;           //p1 and p0 direction output, Data line
     pd0 = 0xFF;
     p0 = 0;       
     p1 = 0;
               
        // Write Data         
        p3_0 = 0;       //Chip select signal assert
        p2 = Reg;       //Register address to p2
        p0 =GpibData;   // Data to p0 (D0-D7)low  //Byte reg Access
        p3_2 = 0;       //Write signal assert            
        Delay(1);       //Delay(1µs)

        p3_2 = 1;       // Write select signal unassert
        p3_0 = 1;       // Chip select signal unasserted      
        
}

[Collin M]

Your read and write routines look a lot better.

I still don't understand the values you are reading at the BSR. When you read 0x5C from the BSR that indicates DAV, NRFD, EOI, and SRQ are asserted which does not make sense.

Can you do an iblines at the host when you read 0x5C from the BSR? Is there a chance your GPIB signals aren't connected correctly? Perhaps some signals are mismatched at the GPIB connector? Can you send me a copy of your schematic showing the TNT5002 and GPIB connector?

Also, it is ok to have DACK# connected to Vcc (V++).

[theotigan]

Read(BSR) = 0x5C

iblines

                                                     EOI ATN SRQ REN IFC NFRD NDAC DAV

                                                      0       0      1       1      0      0          0       0

shematic in the next post.....

thanks

[theotigan]

Mr Collin

Can't i post a Orcad Datei i make the schematic whit Orcad..

Thanks....