Lv 1.1, USRP 14.5.1, 120 MHz Project, FPGA Build Error, Timing violation

[EtuelDue]

Hello.

I am using the LabVIEW CSDS 1.1 and the USRP Driver 14.5.1. Recently I tried to use "PC USRP RIO 120 MHz BW Single-Device Streaming"-Example. As shown in the picture below I added a simple OFDM TX Multiratediagramm (20 MS/s) with a clock of 200 MHz.

After trying to build the FPGA image I get the Build Error "Design did not meet timing. Reduce the data with the longest delay." As shown in attached screenshot the longest route refers to the main loop. Although I only added about 3% of new FPGA elements (Before: Register: 11, DSP: 18, BlockRAM: 16, LUT: 12 After: Register: 13, DSP: 18, BlockRAM: 20, LUT: 15) the main loops routing not possible.

My questions are now:

1) How can I even add more functions to the FPGA, if there are routing problems while only adding some very resourcefunctions? 

2) In the window "Timing Violations" the error is, that the requirement of 500 ns is missed but the total delay of logic and routing is only 440ns. This doesn't make much sense too me.

Thanks and Regards

[Ben_Co]

Hi there EtuelDue,

Sorry to see you're facing these issues! Let's see if I can provide some assistance.

1. A good place to start for creating your own FPGA Functions would be with user Tcap's Community Post found here: https://decibel.ni.com/content/docs/DOC-4355. That example goes through how he developed a FFT function on the FPGA.

2. I definitely agree that that requirement vs. your delay is strange, that's unexpected behavior. Would it be possible for you to post your project so I can try and recreate that behavior? Have you tried recompiling the code several times? This error is thrown when compiling the logic constraints on the FPGA clock; the clock in the timed loop can't have multiple clock pulses before the code inside the loop has fully executed. What are the inputs and outputs of the reads and writes in the timed loop passing?

I see that you're using the Data Clock in that timed loop, could you try creating a 20MHz FPGA clock and use that to time the loop? Data Clock will run at the sampling rate of the device, which might be causing the timing issues.

Finally, could you include the delay underneath "Optimized or Non-Diagram Logic", and the information the "Investigate..." button provides? Maybe that will provide some more insight.

BeenCoughin

[EtuelDue]

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BeenCoughin wrote:

2. I definitely agree that that requirement vs. your delay is strange, that's unexpected behavior. Would it be possible for you to post your project so I can try and recreate that behavior? Have you tried recompiling the code several times? This error is thrown when compiling the logic constraints on the FPGA clock; the clock in the timed loop can't have multiple clock pulses before the code inside the loop has fully executed. What are the inputs and outputs of the reads and writes in the timed loop passing?

I see that you're using the Data Clock in that timed loop, could you try creating a 20MHz FPGA clock and use that to time the loop? Data Clock will run at the sampling rate of the device, which might be causing the timing issues.

Finally, could you include the delay underneath "Optimized or Non-Diagram Logic", and the information the "Investigate..." button provides? Maybe that will provide some more insight.

BeenCoughin

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Hello BeenCoughin,

thank you for your time. I uploaded my project so hopefully this will also answer your last question. I recompiled it several times and either my OFDM MRD or the main loop outputs a Timing Violation Error. The Input and Outputs are the normal U32-Symbols. Where do you want me to apply the 20 MHz Clock? If I understand you correctly you want me to apply the Data Clock to the MRD and the main loop and 20 MHz to the loop containing the FIFOs?

Edit: Uploaded file to big, so I uploaded it to gigamove: https://gigamove.rz.rwth-aachen.de/d/id/UMcKb8AyetDTpV

Regards

[Ben_Co]

Hi EtuelDue,

Thanks for posting your project. I was able to download it and compile the FPGA Build Specification on the Cloud Compile Server and our local compile farm.  This leads me to believe that your software might be corrupted.

Could you please try repairing your installations of LabVIEW Communications, USRP, and Vivado? Can you also try compiling on the Cloud Compile Server? http://www.ni.com/white-paper/52328/en/

These options can be found in the Compiler Preferences Section of the Ribbon when selecting an FPGA Build Specification in the System Designer.

Please let us know how this works out.

Thanks,

BeenCoughin

[EtuelDue]

Hi BeenCoughin,

I can try compiling on the Cloud Compile Farm. Did you use Communictions 1.1, USRP 14.5.1 drivers? Can you also tell mich which compiler you used locally (Vivado)? 

Regards,

Etuel

[Ben_Co]

Hey Etuel,

I used LabVIEW Communications 1.1 and USRP 15.0. The local compiler is Vivado, that is the one that would need to be repaired. Additionally, you may see faster compile times with the Cloud Compile. That being said, please still repair that installation. 

BeenCoughin

[EtuelDue]

Sorry for the long wait, here are my results:

• Using the Cloud Compile Server: No Problem.
• Reinstalling the LV 1.1, 14.5.1 Drivers, Vivado 2013.4 + 64-Bit: No Problem.
• Updating 14.5.1->15.0 and installing Vivado 2014.4: Error

So from my point of view and your description the USRP drivers are fine but using Vivado 2014.4 compiler will result in an error for whatever reason.

Regards

[National_Burritos]

Hi EtuelDue,

Only Vivado 2013.4 is supported by LabVIEW Communications 1.1, which is likely why you are seeing the problem with that version! To my understanding, the differences between versions were not so different that it would affect your compile!

Cheers