LabVIEW Communications System Design Suite

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UI responds very slowly when opening some projects

Dear Community,

 

I am using Labview Comms 1.1 with the FPGA on USRP 2943R. The software responds very slowly during opening and editing some projects, and when I look at the task manager I can see the labview comms process hops between running and not responding. My PC runs 64bits Win7 with I7 core and 8G RAM. Is there anything I can do to improve the performance? Many thanks!

 

Regards

Yi Chu

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This has happened to me all the time. As your project grows, the startup time also increases...

You can delete the *.lvcodeddb and *.lvsuo files in your project directory. Deleting these files will reduce the startup time significantly.

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Thanks very much for the advice! I have made a copy of my project and deleted these two files. However the startup is still quite slow and these two files are generated again, with increasing size... By the way my original .lvcodedb file is almost 200 MB...

 

Regards

Yi Chu

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Hello Yi,

 

Thanks for posting. I am sorry that you are experiencing this behavior.

 

The performance of LabVIEW Communications can vary between machines. It depends on your system specifications, the number of applications open, the number of services being run, the amount of available memory on your computer, etc. 

 

In general the larger the application, the more information needs to be stored in memory, which negatively impacts the speed of the program.

 

If possible, I recommend minimizing the size of your project and reducing the number of open applications.

 

Would you be willing to post your project here so that I can see if I experience the same behavior?

 

Regards,   

Thomas C.
FlexRIO Product Support Engineer
National Instruments
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Hello Thomas,

 

Thanks for the advice! I have attached my project here, it's around 25MB after removing the big .lvcodedb file. However when I open some big example projects (eg. SISO TDD OFDM on NI USRP RIO which is around 140MB) it's not as slow as mine, I'm new to this tool and not quite sure why. I am now compiling the top level FPGA VI of this project and it has been in synthesizing stage for over 20 hours, is this normal? Thanks very much!

 

Regards

Yi Chu

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