07-08-2015 11:47 PM
Hi guys,
Have you ever wondered how exactly this OFDM transmission manage to implement timing and CFO synchronization between the TX side and the RX side?
I've checked every detailed files of the SISO OFDM TDD Demo powered by LV-Comms and USRP-RIO. Though it work well in a single device in the OTA Loopback mode, I failed to find any timing and CFO extimation operation either in the FPGA VIs or in the HOST VIs, which is counter-intuitive since this is the very first step in a real-world wireless transmission.
In this implementation, the RX side performs CP removing directly on the raw samples fetched from the rx_samples_00 FIFO. The question is , how do you make sure that this operates right on the start index of the fetched signal?
Thanks for any advice and comments.
07-09-2015 07:39 AM
08-07-2015 02:52 AM
Thanks for your kindly replay in the beginning!
But I sitll failed to find a CFO correction Block in my version of the SISO OFDM TDD Demo, which was downloaded here:https://decibel.ni.com/content/docs/DOC-40747
As can be seen from above, it simply does CP removing followed by FFT operation.
On the other hand, there seems to be a trick in CTO operation. In the Over-the-air Loopback mode (single device as below), it actually use FIFO trigger control rather than traditional slide-window correlation to decide the starting point for FFT. In this kind of implementation, a timing_pulse trigger_module and a pulse_delay module are involved and another write_N_samples module is use to control FIFOs. I'm not clear how all this works, can anyone out there take a look?
08-14-2015 04:01 PM
Sorry I thought you were referring to the guided help exercise where we have an OFDM TX/RX which does the fractional CFO and timing adjustment on the multirate diagram. In case you're curious, look at Learn > FPGA Design Flow 4th exercise.
For the TDD OFDM Example, the timing adjustment is done on the host instead, but there is currently no CFO correction. Hence, we recommend having the 295x versions (which has a ocxo clock reference rated at 25 ppb) or having a common 10 MHz clock reference when using this example.
If you look at Host.gvi, you'll see some code on PSS sychronization:
which adjusts the timing on the FPGA: