Hello Brooksprumo,
Can you please explain more about the nodes used in the required clock driven loop in the FPGA VI ?
What is the functionality of the four FPGA I/O write Nodes ?
Do they allow the FPGA to write samples coming from external signal sources through the 4 USRP ports ?
If it is correct, are the written signal samples downconverted to baseband automatically ?
What is the function of an FPGA I/O read node ?
Does it read values from the host ?
kindly,
Ali
