cRIO-9058 FPGA timing violation

[Robert_North]

We have recently transitioned from the cRIO-9068, which is reaching its end-of-life this year, to the cRIO-9058. As a result, we need to migrate our existing FPGA design and real-time (RT) code, both of which are currently functioning as expected, to the new hardware platform.
Our initial step involved porting the FPGA design and attempting to build it using the LabVIEW 2025 Q3 64-bit development environment. However, we are encountering timing violation errors during compilation, as shown below.
Could anyone assist in resolving these timing issues?

Regards,

Rob

[wsimpson0050 · Accepted solution]

Hi Robert, could you post an image, or even better drop in your FPGA.VI. If your application involves precise timing of data, try implementing shift registers to break long combinational paths. 

You might try to give this a read and see if it helps: Understanding Timing Considerations for FPGA VIs - NI.

[Robert_North · Accepted solution]

Thank you for the feedback. It pointed me in the right direction. My FPGA now builds correctly.

The solution was to change the FPGA build spec as shown below. I additionally made use of the suggestions in Timing Violations Errors During NI FPGA Compilation - NI to make some improvements to my code which included addressing casting issues and using the smallest data types possible specifically for loop timers used in this design. 

Thanks again for your assistance. It is very much appreciated.

Regards,

Rob

[wsimpson0050]

Awesome! thanks Robert, you might have just taught me something as well.