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3 Kudos
crossrulz

Save FIFOs in a library

Status: New Submitted by Knight of NI Knight of NI on 05-21-2010 11:21 AM Comment
I have several projects that use the same code modules.  FIFOs are used to communicate with these modules.  It would be really nice if I didn't have to keep recreating the same FIFOs for each new project just to be able to reuse my modules.  I suggest being able to save FIFOs (DMAs also) in a lvlib file, similar to project variables in the Windows LabVIEW.
2 Kudos
Harlequinade

Minimize FPGA Compile server to icon

Status: Completed Submitted by Member on 05-06-2010 08:03 AM 2 Comment

Having two computers, one for developing and one desktop pc for administrative work, I use the desktop as compile server for compiling the FPGA VIs. The compilation takes about 45 minutes, during which I can't develop anything in LabVIEW. By sending the data to the desktop pc, I can resume my work. Though on the desktop machine it's annoying to always leave this program open and get closed accidentally from time to time or I forget to start it in the morning after booting the pc.

 

Suggestions:

- Minimize the LabVIEW FPGA Compile Server to system icon tray

- Option for starting the Compile Server on booting of the OS. 

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23 Kudos
Spectre_Dave

Sort Controls in Read / Write Control (FPGA Interface)

Status: New Submitted by Active Participant on 04-02-2010 11:51 AM 3 Comment

The Control / Indicator pull down menu gets unwieldy with a lot of Controls on the FPGA Front Panel. 

 

I would like to be able to sort the names alphabetically so they are easier to pick in the pull down list.

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2 Kudos
Spectre_Dave

Connector Name

Status: New Submitted by Active Participant on 03-11-2010 10:01 AM 3 Comment
I would like a way to name all of the connector I/O from an external souce - perhaps an excel file.  I envision importing a single file for all of the I/O.
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4 Kudos
manu.NET

Time unit converter for Laview FPGA ...

Status: New Submitted by Active Participant on 02-24-2010 09:30 AM 2 Comment

It would be nice to have "time unit converters" in the Labview FPGA Timing menu.

 

My need would be, to automatically, convert Ticks to µs, according to the local Clock cycle frequency ...

 

  • Ticks -> µs
  • µs -> Ticks
  • Ticks -> mSec
  • mSec -> Ticks

 

Using this kind of automatic converters in place of "manual calculations with constants" would help during code evolution ...

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6 Kudos
manu.NET

Configurable timout input unit for Wait on ... I/O method.

Status: New Submitted by Active Participant on 02-24-2010 09:06 AM Comment

The actual "Wait on ... I/O method" has an input named Timeout ... With no unit !

 

Wait on I_O.PNG

 

So i went on the NI forum and i found this article ... http://digital.ni.com/public.nsf/allkb/0D8325309894115286256F3B00341159

 

It would be nice to add the unit in the name of the input parameter like Timeout(ticks)

 

Better idea ... it would be nice to be abble to configure the timout unit like timing objects like this ...

 

Wait on I_O_2.PNG

 

 

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6 Kudos
muks

RT Node

Status: New Submitted by Proven Zealot on 11-25-2009 03:09 AM 1 Comment
Like a Formula node or a math script node why not a RT node that will support Verilog and VHDL? Yeah yeah i know the time taken to code will take a hell a lot of time compared to what can be sweetly done in lv (So dont compare) but at times verilog support will have its advantage.
79 Kudos
gsussman

Simplify the display of Single Cycle Timed Loops in LV FPGA

Status: New Submitted by Active Participant on 10-16-2009 10:39 AM 9 Comment

Single cycle timed loops are a huge performance enhancer in LV FPGA. We learn to use these very prolifically in and around our code to save precious FPGA space, yet the BD representation of the SCTL is the standard Timed Loop structure, with both the Left and Right "ears" visible as well as the conditional terminal.

I propose that the SCTL be given it's own representation on the block diagram, one without the "ears" and without the conditional terminal (by definition it only runs once). This will promote much cleaner looking FPGA code and more readable diagrams.

 

SCTL.PNG

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32 Kudos
gsussman

Better/Faster access to data representation configuration when working with fixed point math

Status: New Submitted by Active Participant on 10-14-2009 05:25 AM 6 Comment

When working with alot of fixed point math (think FPGA development), unless you are content to simply let LabVIEW decide what precision you want in your fixed point data types, it is extremely cumbersome to (right click->properties->Output Configuraton->Uncheck Adapt to source......, close window, move to next function and repeat and repeat and repeat. This is especially true if you end up needing to highly optimize your code.

 

It would be nice to have something like a floating window that could be opened that would display the output configuration data for the selected function or control and allow editing without the need for multiple mouse clicks. The window would automatically update with the configuration of whatever function or control was currently selected.

 

fixed point config.PNG

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4 Kudos
CyGa

Add a common part for FPGA Palette

Status: New Submitted by Active Participant Active Participant on 06-03-2009 07:18 AM 2 Comment
Currently, FPGA palette is specific to target use din the LV project. It could be a great idea to have a common part in this palette to add drivers/functions without regarding target type.