LabVIEW FPGA Idea Exchange

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Select in SCTL

Initially I looked around for my previous idea here: Selecting between two I/O refnums not allowed because I thought it was the same and intended to post a comment to that, but I see that was a bit more specific.

This seems like a more allowable case - why is A forbidden and B perfectly ok?

Select node in SCTL

Case Structure to choose between two values based on boolean input

Here A is forbidden (at Intermediate file generation - so perhaps this would help: Unsupported nodes inside for loop within SCTL should result in a broken VI (NXG != Already Implemented really...)) but B is compiled with no problem. I really don't see why Select of two integers is different to a Case Structure with two integers input, a boolean case selector, and an integer output from the two inputs...

As an idea rather than a rant, I'd like A to be possible.

Number to Boolean Array and Boolean Array to Number along with array manipulation functions (index, replace, reverse) are commonly used methods in FPGA for doing bit manipulation on arrays of integers inside SCTLs. Not having access to these functions is prohibitive and results in having to write code like this:

This becomes very unwieldy when dealing with arrays of 20+ elements. If Number to Boolean Array and Boolean Array to Number are truly no-op elements, then they (along with basic array manipulation nodes) should be added to the list of supported nodes inside for loops inside SCTLs.

The document High Performance FPGA Devleoper's guide lists a parallelized bubble sort. I tried this out, and found that it actually doesn't work. This this matrix successfully gets the max value on top, and the minimum value on the bottom, it doesn't completely sort the values between.

Bubble Sort.JPG

In this example, if the highest value started at the end of the array (red), and the 2nd highest value started 2nd from the end (pink), the high value ends up at the top, and the 2nd highest value ends up 3rd from the top.

Bubble Sort - Markup.JPG

This lattice can be completed to sort the middle sections by adding 3 more columns, one with 3 Min/Max blocks comparing the center 6 values, one with 3 Min/Max blocks comparing the center 4, and a final Min/Max operation comparing the middle 2. This will complete the sort, but will take 7 sequential steps instead of the 4 listed. The following works to sort the entire array:

Bubble Sort - Corrected.JPG

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When debugging, I find it useful to have Graphs on my FPs. Mostly for running in simulation mode but sometimes I want to verify that the compiled code behaves the same way.

I currently have to replace all of my Graphs (fed with fixed size arrays) with Arrays since I can't define the FP element to be a fixed size, unlike arrays. This makes debugging a bit more of a pain than it needs to be.

Is it possible to gbet the option to define a Graph as being a fixed size so that this replacement step is unneccessary?

Tell us why an FPGA needs to be recompiled

The error "You must recompile the VI for the selected target" appears for reasons that, to me, are often obscure or even inexplicable. Recompiling is, as we know, painful. It would be good if the error message included the reason(s) for refusing the existing bitfile, since then I may be able to work out how to stop it happening.

I understand the message comes because LabVIEW decides there are "dirty dots" associated with the bitfile, what I would like the error message to tell me is which dots are dirty and why.

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NI USB-78xxR use 325T FPGA

Hello,

Recently, Last year, i've had a bad experience, when i tried to compile my old FPGA applications with Windows 10.

=> The FPGA ISE XILINX compiler is no more compatible with Windows 10.

Will something be done ? I got no clear answer from NI support ...It should be a XILINX problem !

The issue is that some products on the NI web site, are sold without clear information about the incompatibility with Win 10 !

Please, add a "clear highlighted Warning" on the product page in order to inform about the problem : On FPGA boards and on CRIO targets ...

Thanks for help.

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Along the same line of thinking as this idea:

https://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Handle-Fixed-Point-Integers-Going-Into-Case-Structures/idi-p/3360844

It would be cool if we got rid of the coercion dot here for smaller integers and integer fixed point numbers as the index for an array.

Smaller integer representation for indexes2.png

As it is, it's hard to tell if the compiler will use the bigger I32 for this.

This behavior would also useful for other integer inputs like the memory address input.

It would be nice if this code:

Case Structure version

could be replaced by this code:

Select version

but doing so gives an edit-time error specifying that "Select: Possiblity of Dynamic Refnum not supported for current target".

Is there a fundamental reason this can't be allowed? The behaviour is presumably the same in each case, and the references are from the same place in both cases. In the case structure, the exact same references that are passed to the Select node are used, with the same True/False choice.

It's not a huge issue, but it would be a nice usability/readability improvement.

In labview it is not allowed to exit SCTL running in an external clock domain. Labview claims it could lead to instability of code due to glitches etc on the external clock.

I propose to leave the option open to the programmer to take that risk, which is not always there. It can lead to better understandable code.

For example I have code where I read data from an NI5752 ADC module and store in in block RAM (32 ADc channels, 32 block RAMs). Reading from that ADC implies acquiring the data in the external ADC clock domain. So, also the writing to memory is in that clock domain.

I needed to implement a function to reset the memory as well. That means writing to that memory. That has to be done in an SCTL in the same external clock domain.

However, this reset function (subVI) can no be inserted in the normal "enable chain" of the main program, since the SCTL can not be terminated and the memory reset subVI never terminates.

Now I had to make an ugly trick to get this done. In the main program I create a dead branch doing the reset. That subVI never stops, but after the reset has been done it send a signal via a FIFO to the "wait reset" subVI in the main enable chain. the wait reset is running in the default clock domain and can exit the wait loop after the reset signal has been received.

However, this trick is not easy to understand from the program. It would have been easier if the reset function (external clocked loop) could have exited by itself and be inserted in the main enable chain. That would have been more logical..

Arising from similar requirements as I have posted many moons ago: HERE.... I naively thought putting a terminal in a disable structure would remove it from the FPGA compile. It doesn't.

Years later, I have developed a nice debug interface for my FPGA code which is becoming more and more modular as I refactor it. I have many sub-modules with their own debug interfaces which can be turned on or off from the top-level VI via LVOOP method injection.

The problem is that I can't really compile my entire FPGA VI with ALL debug paths enabled as this just won't fit (It will sometimes compile, but most often not and our FPGA code base is still growing). And this is before I even think about making my debug information more detailed. I would like to be able to easily switch certain aspects of the debug interface on and off as testing requirements change. On the debug interface level I can do this easily by simply not reading the data from the objects being used for the data transfer or simply passing in abstract methods which don't actually do anything and get optimised away. But I'm left with a load of FP controls which are still eating up resources on the FPGA target. I don't want to delete the controls because that leads me to X copies of ever-so-slightly out-of-sync versions of my test VI which quickly becomes a maintenance nightmare. Instead, I want to be able to "easily" reconfigure my test front-panel to only compile the stuff I'm currently actually interested in.

Part of what I would like is the ability to actually define areas of the FP which are enabled, disabled or enabled (and preferably also based on whether simulation is active or not - hence conditional disables for FP). This way, when compiling, the FP elements will actually disappear and full resource savings can be made (as Xilinx is clever enough to optimise away any pointless code LV may stillhave instantiated in VHDL). In addition, the ability to define certain controls as being enabled only when in simulation mode can allow us to have SGL graphs and so on present when needed during debugging.

So, would having conditional disable options for the FP (where controls are shown as greyed out when not available) be of interest to anyone? If this would be an FPGA only thing, I wouldn't shed and tears.

Am I the only one who would use this? hmm. Maybe.

Xilinx supports BRAM primitives (FIFO and normal BRAM) with certain varying width read and write ports. For some applications, the ability to write 2x 16 bit values to a FIFO in one loop and read 1x 16 bit value from the FIFO at double clock rate in another loop can be very useful.

As it stands, the IPCore for such BRAM primitives, although present in LabVIEW FPGA, cannot be used without a CLIP (essentially making this aspect of the IPCore useless).

It would be cool if LV would expose the ability to have differing read and write port widths for BRAM.

Scan Interface for R-Series Devices

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LabVIEW FPGA Idea Exchange

Select in SCTL

For loops inside SCTL should support Number to Boolean Array and Boolean Array to Number

Unsupported nodes inside for loop within SCTL should result in a broken VI

Math Error in Lattice Bubble Sort in High-Performance FPGA Developer's Guide 1.1

Stop disconnecting typedefs in Register Items, Memory Items, FIFOs, and Handshake Items

Colour coding for Estimated and Final timings

Do Not Compile Sequence Structures Inside Single-Cycle Timed Loops

Fixed size Graphs for Debugging (similar to fixed size Arrays)

Tell us why an FPGA needs to be recompiled

NI USB-78xxR use 325T FPGA

LabVIEW FPGA ... limited only by Windows 10 !!!

Get rid of coercion dot when using a smaller integer for index

Selecting between two I/O refnums not allowed

Externally clocked Timed loops : Allow exit

Conditional Disable options for Front Panels of FPGA VIs

BRAM Primitives with different Read / Write data widths

Scan Interface for R-Series Devices

Please add FIND ALL functionality for Memory, Register, and FIFO items

LabVIEW FPGA properties Custom Control Data Type dialog boxes need to show the path and name for the last configured .ctl

Wait until more than one IRQ has occured