LabVIEW FPGA Idea Exchange

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Boolean array to FXP

When parsing message packets in my FPGA code I'm often using a custom packing method with multiple individual datasets being packed into a single U64 (for example) for transport.

With the introduction of Malleable VIs, I would love to be able to create my own packing and unpacking Malleable VIs but don't yet see how. Problem is that the "Boolean array to Number" does not allow attaching a datatype like the "To FXP" does. I would like to marry these two functions into a "Boolean array to FXP" node where I can wire in my input datatype and have the output datatype automatically maintained in a malleable VI.

The error cluster has a string to identify where the error occurred, "source". In a FPGA code the string is only accepted (no broken run arrow) inside an error cluster. I guess this is implemented in this way to maintain code compatibility when you move code to another kind of target. The problem is that doesn't matter what you write in these strings when you are in a FPGA environment, it's ignored.

Some people use the same error code to show a kind of error changing only the source to identify where. I got a software, written by somebody else, that used error code 5000 in all user defined errors, changing only the "source" string. That give me no clue where the error was happening.

Since in a FPGA target only the "code" is useful i a error cluster, I propose two solutions:

1) A warning when a string in a error cluster is not empty (compilation time);

2) The FPGA compiler converts the ASCII chars in "source" string of the error cluster in a fixed size array of bytes [U8]. This array will be converted into a string in a target that can handle it. This is very common when you read a error cluster indicator in a FPGA VI from a RT VI. This solution will have a little overhead but it maintains 100% compatibility.

I like the second solution a bit more. A limited number of characters should be allowed order to save memory. One solution to that is to have a configurable option to determine how many chars is the maximum allowed.

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I love using enums because they can often make discrete options much clearer. Example:

enum clarity.PNG

But, at least as of 2017, the below code is going to use fewer resources and propagate faster because LabVIEW is going to use an 8 bit register above instead of the two bits below.

My solution is to allow smaller integer representations of enums (I'd use a U2 in the above case).

Ideally the user wouldn't even have to specify the integer size, it could just calculate the minimum at edit time and show the user what it is.

VBAT Requirements of sbRIO-9651(SOM)

VBAT input voltage in VBAT Requirements of sbRIO-9651(SOM) should support less Voltage.

SPECIFICATIONS NI sbRIO-9651

http://www.ni.com/pdf/manuals/376962b.pdf

VBAT is for keeping the time on RTC.

Minimum of VBAT input voltage in specification is 2.875V.

In general, the button cell is used to keep time like a Mother board of PC.

For example, CR type Lithium button cell has Nomal voltage 3V and End-point voltage 2.0V.

In this case, if we follow the specification, we can not use this CR type lithium button cell . Many users would like to use this CR type button cell for RTC. So, if we can chang the specification of Minimum VBAT voltage from 2.875V to less 2.0V, it is easy to use in many cases.

Currently, in LabVIEW you can right click a VI's icon at the top right of the front panel to find all instances including where the VI is referenced in a static reference node. Also, when you use have a "Open FPGA VI Reference" in "build specification" or "VI" mode, you can double click the node to open the referenced block diagram. Once the FPGA front panel is open, there's no easy way to get back up to the caller. It would be cool if we could extend the right-click-find-all functionality so that when you right clicked a top level FPGA VI, it would search where that VI was referenced in any "Open FPGA VI Reference" nodes. Currently, when you right click and search, it just says no instances found.

Addtional "Interactive" FPGA mode

When debugging FPGA code, I still like creating debug code right there in the FPGA code with FP debug indicators. After some simulation I can then compile (the exact same code) and test with hardware.

The IDE, however, makes my life really hard. In the background, each VI has a default build spec or bitfile associated with it. When a tiny tiny change occurs in the source code (some of which seem overly sensitive BTW) the interactive mode will not start.

It would be nice if we had the option, assuming that the FP controls are identical, that we can start an interactive mode where the existing bitfile is used with the same FP of the VI source. A visual indicator that the bitfile MAY NOT be identical with the code would by a good idea. Sometimes changes are trivial, sometimes when fixing a bug, we might want to double-check old behaviour for a moment before starting a compile process. The ability to maintain the option to execute the last compiled code seems like it would be a nice addition.

And yes, we could make a RT app which interacts with the FP elements but since debugging code changes often (including FP elements), this is a problematic maintenance issue.

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Floating point FXD

I find that I'm using large bit FXD to handle the dynamic range, but I only have 8 or 16 bit significant bits. I have an I2S input of 24bit numbers that I store in memory as U16 with the following incoding Number = A*2^(B), where A is a FXD(+/-11,9) and B is a FXD(+/-5,5). A and B are bit spliced array that form the U16. This allows me a 33% memory reduction covering a greater dynamic range by trading off resolution. Here the I2S input allows the counting of leading zeros or ones to create the number B and conversion back to 24bits is easy. Three items would make this a great help: 1. a typedef, 2. a quick forward convertor from standard form to FP FXD, and 3. gain inputs on math elements such as FFT if they canhandle FP values.

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Intermediate file generation in parallel

Allow raw access to sbRIO Analog IO

Please give us FXP-based enums

When instantiating case structures, the bit width of the selector has an influence on the efficiency of the code being produced. Of course various compiler optimisations will (may?) do a lot of this lifting for us if we actually wire in an FXP (which LabVIEW again tries to coerce to I32, but that's another battle) but I'd like to have the ability to create, use and convert to and from enums with variable bit-widths. Of course the only parameter of importance for this is the width of the FXP, the integer bits become essentially irrelevant.

I currently have to do a lot of U8 Enum FXP conversions in order to be able to force my case structures to adapt to a given width when supplying an enum to control some code. Readability would benefit greatly if the enum itself could "simply" be an FXT to begin with.

Derived clock instantiation

I don't like static resource definitions FIFOs, Block RAMs or DMAs in my projects. I prefer to have the code declare such entities as they are required because this makes scalability much easier to achieve.

For FIFOs, BlockRAM and so this is no problem, but there are two things we currently cannot instantiate in code:

DMA Channels

Derived clocks

To deal with the seond option: Why is it currently not possible to create a derived clock in code. The ability to automatically have one piece of code accept a single clock reference and let one loop run at a multiple of the speed is something I've wanted to be able to do in the past but it is currently impossible in LabVIEW.

Please let us configure / define derived clocks in LV code.

DMA Channel instantiation

For FIFOs, BlockRAM and so this is no problem, but there are two things we currently cannot instantiate in code:

DMA Channels

Derived clocks

To deal with the first, why can't we define a DMA channel in the code? When parsing the code before compiling, the presence of a DMA channel can be autodetected and added to the interface for the Bitfile.

To try to decouple my code from static DMAs, I actually have started defining my core FPGA VIs as accepting FIFOs with Write functions (For DMAs to host) or Read functions (for writing to FPGA) required. I can then, without having to change my project, wrap this FPGA VI in another VI which can then input wither a DMA channel (which unfortunately must be defined in the project) or a standard FIFO which cen then be used for debugging.

Please allow for the instantiation of DMA channels in code.

More detailed Xilinx log feedback

In correlation with another general idea I have posted, I have come to the conclusion that it would be nice to run an analysis of the Xilinx log in order to give feedback over which code has been constant folded by the Xilinx compiler.

Other aspects such as specific resource utilisation would be really cool also (SRL32 vs Regsiters for Feedback nodes). This would obviously be a post-bitfile operation but could at least give some direct feedback as to what the Xilinx compiler has modified in the code (Dead code elimination, constant folding etc.).

NI has released an exciting new product with the High-Speed Serial board which is essentially a Kintex 7 with GTX transeivers exposed.

https://www.ni.com/en-us/shop/model/pxie-6591.html

https://www.ni.com/en-us/shop/model/pxie-6592.html

Some applications we are working on would benefit greatly from having some way to expose the GTP / GTX / GTH transceivers ont he various NI FPGA boards to enable high speed serial transmissions on a wider product palette. Even the Virtex 5 supprts up to 16 GTP transceivers. Having even 8 of these available for Aurora communication would be a complete game changer as we could move over to optical links between individual devices.

In order to be able to make proper use of this, NI needs to offer GTX / GTH / GTP options for many of their boards. Imagine the power which could be unlocked by itnerfacing 8x Zynq 7010 boards with a single Kintex 7, each Zynq performing some aspect of pre-processing (Analog control, switching, some aspects of control) before sending results back to the Kintex 7..... For those of us working in Scientific areas, the prospects of a system like this is truly mouth-watering.

LabVIEW FPGA Idea Exchange

Boolean array to FXP

The text in the "source" component in a error cluster is useless in a FPGA VI

Allow smaller integer representations of enums

VBAT Requirements of sbRIO-9651(SOM)

Extend right click find all instances functionality to finding where the FPGA VI is opened

Addtional "Interactive" FPGA mode

Display max clock rate that can be achieved during development itself

Remove Stacked Sequence Structure from the FPGA palette

Floating point FXD

Make FPGA Registers searchable and Quick dropable

Labview FPGA CLIP node support for single precision

Intermediate file generation in parallel

Allow raw access to sbRIO Analog IO

Please give us FXP-based enums

Derived clock instantiation

DMA Channel instantiation

Handle Fixed Point Integers Going Into Case Structures

More detailed Xilinx log feedback

Expose Serial transceivers for FPGA boards

Allow Analog IO nodes in SCTL