I don't know if this idea has appeared before, but for me it looks interesting enough to be presented even again.
Now the sequence structure takes a lot of place in the block diagram.
Why not utilise modified error wire to impose the flow instead? The modification would be that potential errors transmitted over this wire would be ignored, if a proper option on the error wire (or in VI or in the environment) will be selected; for example: impose flow only or ignore the errors.
I'm aware that the proposition of an option of automated ignoring the errors in error wire doesn't sound good. I agree that there is a good practice that error should be rather displayed and captured quickly than ignored and forgotten. And I'm aware that developers can explicitly break the error wire within the VI which effectively do the job: impose the flow with ignoring errors.
However, the reason of this proposal is to speed up the code development based on the native LV paradigm of the dataflow. It would be much quicker to build the application in quick and dirty style by not introducing the space consuming structures as the sequence structure is (BTW: I'd still recommend to leave the stacked sequence structure) and spending the time dedicated for development and solving real world problems for trying to fit and extend the structure and VIs within and around it.
For me ignoring the errors on the error wire option would be a natural option. Maybe a bit semantic should be involved here as well for better naming and description, but I think the idea is good enough to be presented.
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